QL5632(2003) Просмотр технического описания (PDF) - QuickLogic Corporation

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QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

PCI Target Interface

Table 11: PCI Target Interface

Signal

Type

Description

Target address, and target Write data During all target accesses, the

address is presented on Usr_Addr_WrData[31:0] at the same time

Usr_Addr_WrData[31:0] O Usr_Adr_Valid is active. During target Write transactions, this port also

presents valid Write data to the PCI configuration space or user logic

when Usr_Adr_Inc is active.

Usr_CBE[3:0]

PCI command and byte enables During target accesses, the PCI

O

command is presented on Usr_CBE[3:0] at the same time Usr_Adr_Valid

is active. This port also presents active-low byte enables to the PCI

configuration space or user logic.

Usr_Adr_Valid

Indicates the beginning of a PCI transaction, and that a target address is

valid on Usr_Addr_WrData[31:0] and the PCI command is valid on

Usr_CBE[3:0]. When this signal is active, the target address must be

O

latched and decoded to determine if this address belongs to the device's

memory or I/O space. Also, the PCI command must be decoded to

determine the type of PCI transaction. On subsequent clocks of a target

access, this signal is low, indicating that address is NOT present on

Usr_Addr_WrData[31:0].

Usr_Adr_Inc

Indicates that the target address should be incremented, because the

previous data transfer has been completed. During burst target accesses,

the target address is only presented to the back-end logic at the beginning

of the transaction (when Usr_Adr_Valid is active), and must therefore be

O

latched and incremented by 4 for subsequent data transfers. Note that

during target Write transactions, Usr_Adr_Inc indicates valid data on

Usr_Addr_WrData[31:0] that must be accepted by the backend logic

(regardless of the state of Usr_Rdy). During Read transactions,

Usr_Adr_Inc signals to the backend that the PCI core has presented the

read data on the PCI bus (TRDYN asserted).

Usr_RdDecode

This signal should be the combinatorial decode of the "user read"

command from Usr_CBE[3:0]. This command may be mapped from any

I of the PCI "read" commands, such as Memory Read, Memory Read Line,

Memory Read Multiple, I/O Read, etc. It is internally gated with

Usr_Adr_Valid.

Usr_WrDecode

This signal should be the combinatorial decode of the "user write"

I

command from Usr_CBE[3:0]. This command may be mapped from any

of the PCI "write" commands, such as Memory Write or I/O Write. It is

internally gated with Usr_Adr_Valid.

Usr_Select

This signal should be driven active when the address on

Usr_Addr_WrData[31:0] has been decoded and determined to be within

the address space of the device. Usr_Addr_WrData[31:0] must be

I

compared to each of the valid Base Address Registers in the PCI

configuration space. Also, this signal must be gated by the Memory

Access Enable or I/O Access Enable registers in the PCI configuration

space (Command Register bits 1 or 0 at offset 04h). Internally gated with

Usr_Adr_Valid.

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