QL5632(2003) Просмотр технического описания (PDF) - QuickLogic Corporation

Номер в каталоге

Компоненты Описание

производитель

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

PCI Master Interface

The internal signals used to interface with the PCI controller in the QL6432 are listed in Table 10

along with a description of each signal. The direction of the signal indicates if the signal is an input

provided by the local interface (I) or an output provided by the PCI controller (O).

NOTE: Signals that end with the character ‘N’ should be considered active-low (for example,

Mst_IRDYN).

Signal

PCI_cmd[3:0]

mst_burst_req

mst_wrAd[31:0]

mst_rdAd[31:0]

Mst_WrData[31:0]

Mst_BE[3:0]

Mst_WrData_Valid

Mst_WrData_Rdy

Mst_BE_Sel

Mst_WrBurst_Done

Table 10: PCI Master Interface

Type

Description

PCI command to be used for the master transaction This signal must

remain unchanged throughout the period when Mst_Burst_Req is active.

PCI commands considered as reads include Interrupt Acknowledge, I/O

I Read, Memory Read, Configuration Read, Memory Read Multiple, Memory

Read Line. PCI commands considered as writes include Special Cycle, I/O

Write, Memory Write, Configuration Write, Memory Write and Invalidate.

Users should make sure that only valid PCI commands are supplied.

Request use of the PCI bus When this signal is active, the core requests

the PCI bus and then generates a master transaction. This signal should be

I held active until all requested data are transferred on the PCI bus and

deactivated in the 2nd clock cycle following the last data transfer on PCI (to

avoid being considered as requesting a new transaction).

Address for master DMA writes This address must be treated as valid

I

from the beginning of a DMA Write until the DMA Write operation is

complete. It should be incremented by 4 bytes each time data is transferred

on the PCI bus.

Address for master DMA reads This address must be treated as valid

I

from the beginning of a DMA read until the DMA Read operation is

complete. It should be incremented by 4 bytes each time data is transferred

on the PCI bus.

I Data for master DMA Writes (to PCI bus)

I Byte enables for master DMA Reads and writes Active-low.

I

Data and byte enable valid on Mst_WrData[31:0] (for master Write

only) and Mst_BE[3:0] (for both master Read and Write)

Data receive acknowledge for Mst_WrData[31:0] (for master

O

Write only) and Mst_BE[3:0] (for both) This serves as the PUSH

control for the internal FIFO and the POP control for the external FIFO (in

FPGA region) which provides data and byte enables to the PCI32 core.

Byte enable select for master transactions When low, Mst_BE[3:0]

should remain constant throughout the entire transfer (when Mst_Burst_Req

I is active) and it is used for every data phase of the master transaction. When

high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of

master Write) is used. Should be held constant throughout the transaction.

O Master Write transaction is completed Active for only one clock cycle.

•

6

•

•

www.quicklogic.com

•

•

•

© 2003 QuickLogic Corporation

Share Link: