ASCELL3912 Просмотр технического описания (PDF) - austriamicrosystems AG

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ASCELL3912

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell

austriamicrosystems AG 

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet

ASCell3912

Austria Mikro Systeme International AG

1.2.4 Receiver Status

Table 3 below shows the format of the state register. Bit b0 is the first which is transmitted by a

readout of the µC. The status register contains the information about a successful received date,

active receiver and the information about the quality of the received signal.

bit #

0

1

[2..3]

Name

DR

RX

RQ[1:0]

Description

Status

Data received a complete L= no data received

message was received H= data received successfully

Receiver is active

L= receiver not active

H= data reception in progress

Signal quality indicates

how many data packets

are necessary for a com-

plete message

L, L (RQ1, RQ0) = 1 packet

L, H = 2 packets

H, L = 3 packets

H, H =4 packets

Comments

Note: This bit is set by the

receiver when 6 bytes of a

packet are correct. This bit in

the status register is neces-

sary for the comfort-orientated

functions of the central locking

functions.

Table 3:

Format of the status register.

1.2.5 µC Interface

The ASCell3912 contains a direct interface to a micro controller (µC). The µC interface of the

ASCell3912 consist of the following five pins:

”Transmit/Received data input/output” (DATA). A bi-directional serial data line, with states ”H”

(recessive, or weak pull-up) and ”L” (dominant).

“Active ”H” transmit data enable” (D_EN)

”Transmit data clock input” (D_CLK).

”Active ”H” µC interrupt output ” (RE_INT).

”Active ”H” µC wakeup output ” (µC_WAKEUP).

”µC clock output ” (µC_CLK).

1.2.5.1

Instruction Set

The following table shows the instruction set of the interface. The first two bits are the operation

code, which determine the direction of the data transfer and which data is transferred.

Operation

code

Instruction or Data

Comment

0

1 LNA FB1 FB0 STR5 STR4 STR3 STR2 STR1 STR0

Write ASCell3912 setup

0

0

Z

LNA FB1 FB0 STR5 STR4 STR3 STR2 STR1 STR0

Read ASCell3912 setup

1

0

Z

DR

RX RQ1 RQ0

Read ASCell3912-State

1

1

Z

B0-b0

B15-b7

Read ASCell3912-Data

Table 4:

Overview of the instruction set.

Rev. A, February 2000

Page 7 of 14

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