DS21554 Просмотр технического описания (PDF) - Maxim Integrated

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DS21554

3.3V/5V E1 Single-Chip Transceivers

Maxim Integrated 

1.2. Document Revision History

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

REVISION

DESCRIPTION

012799

012899

020399

Initial release

Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz

timing

Corrected definition and label of TUDR bit in the THIR register.

021199 Corrected address of IBO register in text.

040199 Added Receive Monitor Mode section

041599

050799

072999

091499

092399

072401

021004

Added section on Protected Interfaces

Corrected pin number and description of FMS in JTAG section

Added list of tables and figures

Added 10mF cap to interface examples

Corrected definition of DS in pin description.

Typo corrected in JTAG Test Access Port Pins.

Added note to the Receive Information Register, FAS Resync Criteria Met.

Corrected Figures 20-1, 20-2, 20-3 with respect to CS.

Corrected typo in Figure 18-14 (RCR1.1 reference corrected).

Corrected formatting issues.

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