DS21554L Просмотр технического описания (PDF) - Maxim Integrated

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DS21554L

3.3V/5V E1 Single-Chip Transceivers

Maxim Integrated 

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

1.1. Functional Description

The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins

of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the

jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the

framing/multiframe pattern. The DS21354/DS21554 contain an active filter that reconstructs the analog-

received signal for the nonlinear losses that occur in transmission. The devices have a usable receive

sensitivity of 0 to -43dB, which allows the device to operate on cables over 2km in length. The receive-

side framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming

alarms including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receive-

side elastic store can be enabled to absorb the phase and frequency differences between the recovered E1

data stream and an asynchronous backplane clock, which is provided at the RSYSCLK input. The clock

applied at the RSYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz clock or a 1.544MHz

clock.

The transmit-side framer is totally independent from the receive side in both the clock requirements and

characteristics. Data off a backplane can be passed through a transmit-side elastic store if necessary. The

transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.

Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In

each 125ms frame, there are 32 eight-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and

received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32.

Time slot 0 is identical to channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or

channel) is made up of eight bits, which are numbered 1 to 8. Bit number 1 is the most significant bit

(MSB) and is transmitted first. Bit number 8 is the least significant bit (LSB) and is transmitted last. The

term “locked” refers to two clock signals that are phase or frequency locked, or derived from a common

clock (i.e., a 1.544MHz clock may be locked to a 2.048MHz clock if they share the same 8kHz

component). Throughout this data sheet, the following abbreviations are used:

NAME

FAS

CAS

MF

Si

CRC4

CCS

Sa

E-Bit

FUNCTION

Frame-Alignment Signal

Channel-Associated Signaling

Multiframe

International Bits

Cyclical Redundancy Check

Common-Channel Signaling

Additional Bits

CRC4 Error Bits

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