DS21554L Просмотр технического описания (PDF) - Maxim Integrated

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Компоненты Описание

производитель

DS21554L

3.3V/5V E1 Single-Chip Transceivers

Maxim Integrated 

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

LIST OF TABLES

Table 3-1. Pin Description Sorted by Pin Number............................................................................................................. 10

Table 3-2. Pin Description by Symbol ................................................................................................................................. 12

Table 4-1. Register Map Sorted by Address ...................................................................................................................... 25

Table 5-1. Device ID Bit Map ................................................................................................................................................ 30

Table 5-2. SYNC/RESYNC Criteria ..................................................................................................................................... 32

Table 6-1. Alarm Criteria ....................................................................................................................................................... 46

Table 14-1. HDLC Controller Register List ......................................................................................................................... 70

Table 15-1. Line Build-Out Select in LICR for the DS21554 ............................................................................................ 81

Table 15-2. Line Build-Out Select in LICR for the DS21354 ............................................................................................ 82

Table 15-3. Transformer Specifications .............................................................................................................................. 82

Table 15-4. Receive Monitor Mode Gain ............................................................................................................................ 89

Table 16-1. Instruction Codes for IEEE 1149.1 Architecture ........................................................................................... 95

Table 16-2. ID Code Structure.............................................................................................................................................. 96

Table 16-3. Device ID Codes................................................................................................................................................ 96

Table 16-4. Boundary Scan Control Bits............................................................................................................................. 97

Table 17-1. IBO Master Device Select ................................................................................................................................ 98

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