DS21554L Просмотр технического описания (PDF) - Maxim Integrated
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DS21554L Datasheet PDF : 124 Pages
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
12. ELASTIC STORES OPERATION...................................................................................... 65
12.1. RECEIVE SIDE .......................................................................................................................................65
12.2. TRANSMIT SIDE.....................................................................................................................................65
13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................. 66
13.1. HARDWARE SCHEME ...........................................................................................................................66
13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME .........................................................66
13.3. INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME....................................................68
14. HDLC CONTROLLER FOR THE SA BITS OR DS0 ......................................................... 70
14.1. GENERAL OVERVIEW ...........................................................................................................................70
14.2. HDLC STATUS REGISTERS..................................................................................................................71
14.3. BASIC OPERATION DETAILS ...............................................................................................................72
14.3.1. Example: Receive an HDLC Message................................................................................................72
14.3.2. Example: Transmit an HDLC Message...............................................................................................72
14.4. HDLC REGISTER DESCRIPTION..........................................................................................................73
15. LINE INTERFACE FUNCTIONS........................................................................................ 80
15.1. RECEIVE CLOCK AND DATA RECOVERY.......................................................................................................81
15.2. TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................................81
15.3. JITTER ATTENUATOR..................................................................................................................................82
15.4. PROTECTED INTERFACES ...........................................................................................................................86
15.5. RECEIVE MONITOR MODE ..........................................................................................................................89
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................... 90
16.1. INSTRUCTION REGISTER.............................................................................................................................95
16.2. TEST REGISTERS.......................................................................................................................................96
17. INTERLEAVED PCM BUS OPERATION .......................................................................... 98
17.1. CHANNEL INTERLEAVE ...............................................................................................................................99
17.2. FRAME INTERLEAVE ...................................................................................................................................99
18. FUNCTIONAL TIMING DIAGRAMS................................................................................ 100
18.1. RECEIVE .................................................................................................................................................100
18.2. TRANSMIT ...............................................................................................................................................104
19. OPERATING PARAMETERS.......................................................................................... 111
20. AC TIMING PARAMETERS AND DIAGRAMS ............................................................... 112
20.1. MULTIPLEXED BUS AC CHARACTERISTICS ................................................................................................112
20.2. NONMULTIPLEXED BUS AC CHARACTERISTICS..........................................................................................115
20.3. RECEIVE-SIDE AC CHARACTERISTICS ......................................................................................................117
20.4. TRANSMIT AC CHARACTERISTICS.............................................................................................................121
21. PACKAGE INFORMATION............................................................................................. 124
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