DS21554L Просмотр технического описания (PDF) - Maxim Integrated
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DS21554L Datasheet PDF : 124 Pages
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
TABLE OF CONTENTS
1. INTRODUCTION.................................................................................................................. 6
1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7
1.2. DOCUMENT REVISION HISTORY .............................................................................................................8
2. BLOCK DIAGRAM .............................................................................................................. 9
3. PIN DESCRIPTION............................................................................................................ 10
3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14
3.1.1. Transmit-Side Pins..............................................................................................................................14
3.1.2. Receive-Side Pins...............................................................................................................................17
3.1.3. Parallel Control Port Pins ....................................................................................................................20
3.1.4. JTAG Test Access Port Pins...............................................................................................................22
3.1.5. Interleave Bus Operation Pins ............................................................................................................22
3.1.6. Line Interface Pins ..............................................................................................................................23
3.1.7. Supply Pins .........................................................................................................................................24
4. PARALLEL PORT ............................................................................................................. 25
4.1. REGISTER MAP ........................................................................................................................................25
5. CONTROL, ID, AND TEST REGISTERS .......................................................................... 30
5.1. POWER-UP SEQUENCE ..........................................................................................................................30
5.2. SYNCHRONIZATION AND RESYNCHRONIZATION...............................................................................32
5.3. FRAMER LOOPBACK ...............................................................................................................................36
5.4. AUTOMATIC ALARM GENERATION........................................................................................................38
5.5. REMOTE LOOPBACK ...............................................................................................................................40
5.6. LOCAL LOOPBACK...................................................................................................................................40
6. STATUS AND INFORMATION REGISTERS .................................................................... 43
6.1. CRC4 SYNC COUNTER............................................................................................................................45
7. ERROR COUNT REGISTERS........................................................................................... 50
7.1. BPV OR CODE VIOLATION COUNTER ...................................................................................................50
7.2. CRC4 ERROR COUNTER.........................................................................................................................51
7.3. E-BIT COUNTER .......................................................................................................................................51
7.4. FAS ERROR COUNTER .................................................................................................................................52
8. DS0 MONITORING FUNCTION ........................................................................................ 53
9. SIGNALING OPERATION................................................................................................. 56
9.1. PROCESSOR-BASED SIGNALING ..........................................................................................................56
9.2. HARDWARE-BASED SIGNALING ............................................................................................................58
9.2.1. Receive Side .......................................................................................................................................58
9.2.2. Transmit Side ......................................................................................................................................59
10. PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 60
10.1. TRANSMIT-SIDE CODE GENERATION ................................................................................................60
10.1.1. Simple Idle Code Insertion and Per-Channel Loopback.....................................................................60
10.1.2. Per-Channel Code Insertion ...............................................................................................................61
10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62
11. CLOCK BLOCKING REGISTERS..................................................................................... 63
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