DS21554L Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS21554L

3.3V/5V E1 Single-Chip Transceivers

Maxim Integrated 

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers

3.1.2.

Receive-Side Pins

Signal Name:

RLINK

Signal Description: Receive Link Data

Signal Type:

Output

Updated with the fully recovered E1 data stream on the rising edge of RCLK.

Signal Name:

RLCLK

Signal Description: Receive Link Clock

Signal Type:

Output

4kHz to 20kHz clock (Sa bits) for the RLINK output. See Section 13 for details.

Signal Name:

RCLK

Signal Description: Receive Clock

Signal Type:

Output

2.048MHz clock that is used to clock data through the receive-side framer.

Signal Name:

RCHCLK

Signal Description: Receive Channel Clock

Signal Type:

Output

A 256kHz clock that pulses high during the LSB of each channel. Synchronous with RCLK when the

receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is

enabled. Useful for parallel to serial conversion of channel data.

Signal Name:

RCHBLK

Signal Description: Receive Channel Block

Signal Type:

Output

A user-programmable output that can be forced high or low during any of the 32 E1 channels.

Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK

when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD

controller in applications where not all E1 channels are used such as Fractional E1, 384kbps service,

768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for

external per-channel loopback, and for per-channel conditioning. See Section 10 for details.

Signal Name:

RSER

Signal Description: Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name:

RSYNC

Signal Description: Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide, is output at this pin that identifies either frame or CAS/CRC

multiframe boundaries. If the receive-side elastic store is enabled, then this pin can be enabled to be an

input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.

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