DS21554L Просмотр технического описания (PDF) - Maxim Integrated
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DS21554L Datasheet PDF : 124 Pages
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Table 3-2. Pin Description by Symbol
PIN
3
13
66
67
68
69
70
71
72
73
11
36
54
75
56
57
58
59
62
63
64
65
44, 61, 81, 83
45, 60, 80, 84
76
25
4
7
10
2
5
12
21
55
8, 9, 15, 23, 26,
27, 28
1
92
6
82
88
89
74
85
97
79
NAME
8MCLK
8XCLK
A0
A1
A2
A3
A4
A5
A6
ALE (AS)/A7
BTS
CI
CO
CS
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
DVDD
DVSS
FMS
INT
JTCLK
JTDI
JTDO
JTMS
JTRST
LIUC
MCLK
MUX
N.C.
RCHBLK
RCHCLK
RCL
RCLK
RCLKI
RCLKO
RD (DS)
RDATA
RFSYNC
RLCLK
TYPE
O
O
I
I
I
I
I
I
I
I
I
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I
O
I
I
O
I
I
I
I
I
—
O
O
O
O
I
O
I
O
O
O
FUNCTION
8.192MHz Clock
Eight-Times Clock
Address Bus Bit 0
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Bus Bit 5
Address Bus Bit 6
Address Latch Enable/Address Bus Bit 7
Bus Type Select
Carry In
Carry Out
Chip Select, Active Low
Data Bus Bit0/ Address/Data Bus Bit 0
Data Bus Bit1/ Address/Data Bus Bit 1
Data Bus Bit 2/Address/Data Bus 2
Data Bus Bit 3/Address/Data Bus Bit 3
Data Bus Bit4/Address/Data Bus Bit 4
Data Bus Bit 5/Address/Data Bus Bit 5
Data Bus Bit 6/Address/Data Bus Bit 6
Data Bus Bit 7/Address/Data Bus Bit 7
Digital Positive Supply
Digital Signal Ground
Framer Mode Select
Interrupt
IEEE 1149.1 Test Clock Signal
IEEE 1149.1 Test Data Input
IEEE 1149.1 Test Data Output
IEEE 1149.1 Test Mode Select
IEEE 1149.1 Test Reset, Active Low
Line Interface Connect
Master Clock Input
Bus Operation
No Connect. Do not connect any signal to this pin.
Receive Channel Block
Receive Channel Clock
Receive Carrier Loss
Receive Clock
Receive Clock Input
Receive Clock Output
Read Input (Data Strobe), Active Low
Receive Data
Receive Frame Sync
Receive Link Clock
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