MPC972
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
MPC972
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
All inputs have internal pull-up resistors (appr. 50 K) except for the xtal1 and xtal2 pins.
Figure 1. 52–Lead Pinout (Top View)
FUNCTION TABLE 1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
0
÷4
0
0
÷4
0
0
÷2
0
1
÷6
0
1
÷6
0
1
÷4
1
0
÷8
1
0
÷8
1
0
÷6
1
1
÷12
1
1
÷10
1
1
÷8
FUNCTION TABLE 2
*fselFB2
fselFB1
fselFB0
QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1
÷10
1
0
0
÷8
1
0
1
÷12
1
1
0
÷16
1
1
1
÷20
*If the fselFB2 is 1, it may be necessary to apply a reset after power up
to ensure synchronization between QFB and the other inputs.
FUNCTION TABLE 3
Control Pin
Logic ‘0’
VCO_Sel
Ref_Sel
TCLK_Sel
PLL_En
MR/OE
Inv_Clk
VCO/2
TCLK
TCLK0
Bypass PLL
Master Reset/Output Hi–Z
Non–Inverted Qc2, Qc3
Logic ‘1’
VCO
Xtal (PECL)
TCLK1
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
2
MOTOROLA