3.0
OutA
2.5
tD = 3.8956
2.0
In
1.5
OutB
tD = 3.9386
1.0
0.5
0
2
4
6
8
10 12 14
TIME (nS)
Figure 12. Single versus Dual Waveforms
MPC972
OUTPUT
BUFFER
7Ω
RS = 36 Ω ZO = 50 Ω
RS = 36 Ω ZO = 50 Ω
7 Ω + 36 Ω k 36 Ω = 50 Ω k 50 Ω
25 Ω = 25 Ω
Figure 13. Optimized Dual Line Termination
SPICE level output buffer models are available for engineers
who want to simulate their specific interconnect schemes. In
addition IV characteristics are in the process of being
generated to support the other board level simulators in general
use.
Using the Output Freeze Circuitry
With the recent advent of a “green” classification for
computers the desire for unique power management among
MPC972
system designers is keen. The individual output enable control
of the MPC972 allows designers, under software control, to
implement unique power management schemes into their
designs. Although useful, individual output control at the
expense of one pin per output is too high, therefore a simple
serial interface was derived to economize on the control pins.
The freeze control logic provides a mechanism through
which the MPC972 clock outputs may be frozen (stopped in the
logic ‘0’ state):
The freeze mechanism allows serial loading of the 12–bit
Serial Input Register, this register contains one programmable
freeze enable bit for 12 of the 14 output clocks. The Qc0 and
QFB outputs cannot be frozen with the serial port, this avoids
any potential lock up situation should an error occur in the
loading of the Serial Input Register. The user may program an
output clock to freeze by writing logic ‘0’ to the respective freeze
enable bit. Likewise, the user may programmably unfreeze an
output clock by writing logic ‘1’ to the respective enable bit.
The freeze logic will never force a newly–frozen clock to a
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at logic
‘0’ once it is there. Likewise, the freeze logic will never force a
newly–unfrozen clock to a logic ‘1’ state before the time at which
it would normally transition there. The logic re–enables the
unfrozen clock during the time when the respective clock would
normally be in a logic ‘0’ state, eliminating the possibility of ‘runt’
clock pulses.
The user may write to the Serial Input register through the
Frz_Data input by supplying a logic ‘0’ start bit followed serially
by 12 NRZ freeze enable bits. The period of each Frz_Data bit
equals the period of the free–running Frz_Clk signal. The
Frz_Data serial transmission should be timed so the MPC972
can sample each Frz_Data bit with the rising edge of the
free–running Frz_Clk signal.
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D0-D3 are the control bits for Qa0-Qa3, respectively
D4-D7 are the control bits for Qb0-Qb3, respectively
D8-D10 are the control bits for Qc1-Qc3, respectively
D11 is the control bit for QSync
Figure 14. Freeze Data Input Protocol
MOTOROLA
11