74LVC1G57-Q100 Просмотр технического описания (PDF) - NXP Semiconductors.
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74LVC1G57-Q100 Datasheet PDF : 16 Pages
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74LVC1G57-Q100
Low-power configurable multiple function gate
Rev. 1 — 15 April 2014
Product data sheet
1. General description
The 74LVC1G57-Q100 provides configurable multiple functions. Eight patterns of 3-bit
input, determine the output state. The user can choose the logic functions AND, OR,
NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
All inputs (A, B and C) are Schmitt trigger inputs that can transform slowly changing input
signals into sharply defined, jitter-free output signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
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