UT621024LC-35L Просмотр технического описания (PDF) - Utron Technology Inc

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UT621024LC-35L

128K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Rev. 1.5

UT621024

128K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

SYMBOL TEST CONDITION

VDR

CE1 ≧ VCC-0.2V or

CE2 ≤ 0.2V

IDR

Vcc=3V

CE1 ≧ VCC-0.2V or

CE2 ≤ 0.2V

Chip Disable to Data

Retention Time

tCDR See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time

*Those parameters are for reference only under 50℃

MIN. TYP. MAX. UNIT

2.0 - -

V

-L

-

1

40 µA

20*

- LL -

20 µA

0.5

10*

0-

-

ns

tRC* -

-

ns

DATA RETENTION WAVEFORM

VCC

CE1

VSS

CE2

4.5V

tCDR

VIH

VIL

Date Retention Mode

VDR ≧ 2.0V

CE1 ≧ VCC -0.2V

CE2 ≤ 0.2V

4.5V

tR

VIH

VIL

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80036

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

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