SAA7126H Просмотр технического описания (PDF) - Philips Electronics
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SAA7126H Datasheet PDF : 44 Pages
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Philips Semiconductors
Digital video encoder
Product specification
SAA7126H; SAA7127H
Table 27 Subaddress 6BH
DATA BYTE
PRCV2
ORCV2
CBLF
LOGIC
LEVEL
0
1
0
1
0
DESCRIPTION
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
pin RCV2 is switched to input; default after reset
pin RCV2 is switched to output
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1 if ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL
PRCV1
ORCV1
TRCV2
SRCV1
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after
reset
1 polarity of RCV1 as output is active LOW, falling edge is taken when input
0 pin RCV1 is switched to input; default after reset
1 pin RCV1 is switched to output
0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset
1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
− defines signal type on pin RCV1; see Table 28
Table 28 Logic levels and function of SRCV1
DATA BYTE
SRCV11 SRCV10
0
0
0
1
1
0
AS OUTPUT
VS
FS
FSEQ
AS INPUT
VS
FS
FSEQ
1
1
−
−
FUNCTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
not applicable
Table 29 Subaddresses 6CH and 6DH
DATA BYTE
HTRIG
DESCRIPTION
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG
decreases delays of all internally generated timing signals; reference mark: analog output
horizontal sync (leading slope) coincides with active edge of RCV used for triggering at
HTRIG = 39H
2002 Oct 15
20
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