SAA7126H Просмотр технического описания (PDF) - Philips Electronics
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SAA7126H Datasheet PDF : 44 Pages
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Philips Semiconductors
Digital video encoder
Product specification
SAA7126H; SAA7127H
Table 21 Logic levels and function of CCRS
CCRS1
0
0
1
1
CCRS0
0
1
0
1
DESCRIPTION
no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5
cross-colour reduction #1 active; for overall transfer characteristic see Fig.5
cross-colour reduction #2 active; for overall transfer characteristic see Fig.5
cross-colour reduction #3 active; for overall transfer characteristic see Fig.5
Table 22 Subaddress 61H
DATA BYTE
FISE
PAL
SCBW
YGS
INPI
DOWNA
DOWNB
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
864 total pixel clocks per line; default after reset
858 total pixel clocks per line
NTSC encoding (non-alternating V component)
PAL encoding (alternating V component); default after reset
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset
luminance gain for white − black 100 IRE; default after reset
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
PAL switch phase is nominal; default after reset
PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 23
DAC for CVBS in normal operational mode; default after reset
DAC for CVBS forced to lowest output voltage
DACs for R, G and B in normal operational mode
DACs for R, G and B forced to lowest output voltage; default after reset
Table 23 Subaddress 62H
DATA BYTE
RTCE
LOGIC
LEVEL
0
1
DESCRIPTION
no real-time control of generated subcarrier frequency; default after reset
real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for
timing see Fig.13
2002 Oct 15
18
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