H8/3060 Просмотр технического описания (PDF) - Renesas Electronics
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H8/3060 Datasheet PDF : 1021 Pages
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9.4 Operation .......................................................................................................................... 311
9.4.1 8TCNT Count Timing ......................................................................................... 311
9.4.2 Compare Match Timing....................................................................................... 312
9.4.3 Input Capture Signal Timing ............................................................................... 313
9.4.4 Timing of Status Flag Setting .............................................................................. 314
9.4.5 Operation with Cascaded Connection.................................................................. 316
9.4.6 Input Capture Setting........................................................................................... 318
9.5 Interrupt ............................................................................................................................ 320
9.5.1 Interrupt Sources.................................................................................................. 320
9.5.2 A/D Converter Activation.................................................................................... 321
9.6 8-Bit Timer Application Example .................................................................................... 321
9.7 Usage Notes ...................................................................................................................... 322
9.7.1 Contention between 8TCNT Write and Clear...................................................... 322
9.7.2 Contention between 8TCNT Write and Increment .............................................. 323
9.7.3 Contention between TCOR Write and Compare Match ...................................... 324
9.7.4 Contention between TCOR Read and Input Capture........................................... 325
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 326
9.7.6 Contention between TCOR Write and Input Capture .......................................... 327
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)........................................................................................ 328
9.7.8 Contention between Compare Matches A and B ................................................. 329
9.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 329
Section 10 Programmable Timing Pattern Controller (TPC) ................................. 333
10.1 Overview........................................................................................................................... 333
10.1.1 Features................................................................................................................ 333
10.1.2 Block Diagram..................................................................................................... 334
10.1.3 Pin Configuration ................................................................................................ 335
10.1.4 Register Configuration......................................................................................... 336
10.2 Register Descriptions........................................................................................................ 337
10.2.1 Port A Data Direction Register (PADDR)........................................................... 337
10.2.2 Port A Data Register (PADR).............................................................................. 337
10.2.3 Port B Data Direction Register (PBDDR) ........................................................... 338
10.2.4 Port B Data Register (PBDR) .............................................................................. 338
10.2.5 Next Data Register A (NDRA) ............................................................................ 339
10.2.6 Next Data Register B (NDRB) ............................................................................ 341
10.2.7 Next Data Enable Register A (NDERA).............................................................. 343
10.2.8 Next Data Enable Register B (NDERB).............................................................. 344
10.2.9 TPC Output Control Register (TPCR)................................................................. 345
10.2.10 TPC Output Mode Register (TPMR)................................................................... 348
Rev. 6.00 Mar 18, 2005 page xvii of xlviii
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