UPC4742GR-9LG Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPC4742GR-9LG

SINGLE POWER SUPPLY, HIGH SPEED, WIDE BAND, DUAL OPERATIONAL AMPLIFIERS

NEC => Renesas Technology 

μ PC842GR-9LG, μ PC4742GR-9LG

<R> PRECAUTIONS FOR USE

O The process of unused circuits

If there is an unused circuit, the following connection is recommended.

Process example of unused circuits

V+

V+

R

−

+

R

To potentials within the range of

common-mode input voltage (VICM)

V−

V−

Remark A midpoint potential of V+ and V− is applied to this example.

O Ratings of input/output pin voltage

When the voltage of input/output pin exceeds the absolute maximum rating, it may cause degradation of

characteristics or damages, by a conduction of a parasitic diode within an IC. In addition, when the input pin may be

lower than V−, or the output pin may exceed the power supply voltage, it is recommended to make a clump circuit by

a diode whose forward voltage is low (e.g.: Schottky diode) for protection.

O Range of common-mode input voltage

When the supply voltage does not meet the condition of electrical characteristics, the range of common-mode

input voltage is as follows.

VICM (TYP.): V− to V+ − 1.8 (V) (TA = 25°C)

During designing, temperature characteristics for use with allowance.

O The maximum output voltage

The range of the TYP. value of the maximum output voltage when the supply voltage does not meet the condition

of electrical characteristics is as follows:

VOm+ (TYP.): V+ − 1 (V) (TA = 25°C), VOm− (TYP.): V− + 0.7 (V) (TA = 25°C)

During designing, consider variations in characteristics and temperature characteristics for use with allowance.

In addition, also note that the output voltage range (VOm+ − VOm−) becomes narrow when an output current

increases.

O Operation of output

This IC will not operate an output current sinking when the output voltage is V− + 0.7 V and below. In this situation,

an output voltage and its level approach to the V− side can be improved by connecting the load resistance to an

output pin / V− intermediate by sinking current at the load resistance side. (The effect will differ depending on the

flow of current in the load resistance.)

O Handling of ICs

When stress is added to ICs due to warpage or bending of a board, the characteristic fluctuates due to

piezoelectric effect. Therefore, pay attention to warpage or bending of a board.

Data Sheet G17932EJ4V0DS

7

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