FSFR2000 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FSFR2000 Datasheet PDF : 16 Pages
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Functional Description
1. Basic Operation: FSFR-series is designed to drive
high-side and low-side MOSFETs complementarily with
50% duty cycle. A fixed dead time of 350ns is introduced
between consecutive transitions, as shown in Figure 16.
High side
MOSFET
gate drive
Dead time
Low side
MOSFET
gate drve
time
Figure 16. MOSFETs Gate Drive Signal
2. Internal Oscillator: FSFR-series employs a current-
controlled oscillator, as shown in Figure 17. Internally,
the voltage of RT pin is regulated at 2V and the
charging/discharging current for the oscillator capacitor,
CT, is obtained by copying the current flowing out of RT
pin (ICTC) using a current mirror. Therefore, the switching
frequency increases as ICTC increases.
Gain
1.8
f min f normal f max
f ISS
1.6
1.4
1.2
1.0
Soft-start
0.8
0.6
60
70
80
90 100 110 120 130 140 150
freq (kHz)
Figure 18. Resonant Converter Typical Gain Curve
LVcc VDL
RT
Rmax
Rmin
Rss
Css CON
Control
IC
SG
PG
Figure 19. Frequency Control Circuit
Figure 17. Current Controlled Oscillator
3. Frequency Setting: Figure 18 shows the typical
voltage gain curve of a resonant converter, where the
gain is inversely proportional to the switching frequency.
The output voltage can be regulated by modulating the
switching frequency. Figure 19 shows the typical circuit
configuration for RT pin, where the opto-coupler
transistor is connected to the RT pin to modulate the
switching frequency.
The minimum switching frequency is determined as:
f min = 5.2kΩ ×100(kHz) (1)
Rmin
Assuming the saturation voltage of opto-coupler
transistor is 0.2V, the maximum switching frequency is
determined as:
f max = (5.2kΩ + 4.68kΩ ) ×100(kHz)
(2)
Rmin
Rmax
To prevent excessive inrush current and overshoot of
output voltage during start-up, increase the voltage gain
of the resonant converter progressively. Since the
voltage gain of the resonant converter is inversely
proportional to the switching frequency, the soft-start is
implemented by sweeping down the switching frequency
from an initial high frequency (f ISS) until the output
voltage is established. The soft-start circuit is made by
connecting R-C series network on the RT pin, as shown
in Figure 19. FSFR-series also has an internal soft-start
for 3ms to reduce the current overshoot during the initial
© 2007 Fairchild Semiconductor Corporation
FSFR2100 • 1.0.0
9
www.fairchildsemi.com
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