K6R4004C1D Просмотр технического описания (PDF) - Samsung
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K6R4004C1D Datasheet PDF : 9 Pages
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K6R4004C1D
PRELIMINARY
CMOS SRAM
1M x 4 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4004C1D-10 : 65mA(Max.)
Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004C1D-J : 32-SOJ-400
K6R4004C1D-K : 32-SOJ-400(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
GENERAL DESCRIPTION
The K6R4004C1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004C1D is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1~I/O4
Clk Gen.
Data
Cont.
Pre-Charge Circuit
Memory Array
1024 Rows
1024 x 4 Columns
I/O Circuit
Column Select
CLK
Gen.
A10 A12 A14 A16 A18
A11 A13 A15 A17 A19
CS
WE
OE
A0 1
A1 2
A2 3
A3 4
A4 5
CS 6
I/O1 7
Vcc 8
Vss 9
I/O2 10
WE 11
A5 12
A6 13
A7 14
A8 15
A9 16
SOJ
32 A19
31 A18
30 A17
29 A16
28 A15
27 OE
26 I/O4
25 Vss
24 Vcc
23 I/O3
22 A14
21 A13
20 A12
19 A11
18 A10
17 N.C
PIN FUNCTION
Pin Name
A0 - A19
WE
CS
OE
I/O1 ~ I/O4
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-3-
Rev. 2.0
July 2004
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