ST7LITEU05 ST7LITEU09
2 PIN DESCRIPTION
Figure 2. 8-pin SO and DIP Package Pinout
VDD 1
PA5 (HS) / AIN4 / CLKIN 2 ei4
8 VSS
ei0 7 PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3 / MCO 3 ei3
ei1 6 PA1 (HS) / AIN1 / ICCCLK
PA3 / RESET 4
ei2 5 PA2 (HS) / LTIC / AIN2
Figure 3. 8-pin DFN Package Pinout
(HS) : High sink capability
eix : associated external interrupt vector
VDD 1
PA5 (HS) / AIN4 / CLKIN 2 ei4
8
ei0 7
VSS
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3 / MCO 3 ei3 ei1 6 PA1 (HS) / AIN1 / ICCCLK
PA3 / RESET 4
ei2 5 PA2 (HS) / LTIC / AIN2
(HS) : High sink capability
eix : associated external interrupt vector
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