BD82HM55QMNT Просмотр технического описания (PDF) - Intel

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BD82HM55QMNT

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

5.17

5.18

5.19

5.20

5.21

5.22

5.16.11.3LED Message Type .................................................................. 201

5.16.11.4SGPIO Waveform .................................................................... 202

5.16.12External SATA...................................................................................... 203

High Precision Event Timers.............................................................................. 203

5.17.1 Timer Accuracy .................................................................................... 203

5.17.2 Interrupt Mapping ................................................................................ 204

5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 204

5.17.4 Enabling the Timers.............................................................................. 205

5.17.5 Interrupt Levels ................................................................................... 205

5.17.6 Handling Interrupts .............................................................................. 206

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 206

USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 207

5.18.1 EHC Initialization.................................................................................. 207

5.18.1.1 BIOS Initialization ................................................................... 207

5.18.1.2 Driver Initialization ................................................................. 207

5.18.1.3 EHC Resets ............................................................................ 207

5.18.2 Data Structures in Main Memory............................................................. 207

5.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 208

5.18.4 Data Encoding and Bit Stuffing ............................................................... 208

5.18.5 Packet Formats .................................................................................... 208

5.18.6 USB 2.0 Interrupts and Error Conditions .................................................. 208

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 209

5.18.7 USB 2.0 Power Management .................................................................. 209

5.18.7.1 Pause Feature ........................................................................ 209

5.18.7.2 Suspend Feature..................................................................... 209

5.18.7.3 ACPI Device States ................................................................. 210

5.18.7.4 ACPI System States ................................................................ 210

5.18.8 USB 2.0 Legacy Keyboard Operation ....................................................... 210

5.18.9 USB 2.0 Based Debug Port .................................................................... 211

5.18.9.1 Theory of Operation ............................................................... 212

5.18.10EHCI Caching....................................................................................... 216

5.18.11USB Pre-Fetch Based Pause ................................................................... 216

5.18.12Function Level Reset Support (FLR) ........................................................ 216

5.18.12.1FLR Steps .............................................................................. 216

5.18.13USB Overcurrent Protection ................................................................... 217

Integrated USB 2.0 Rate Matching Hub .............................................................. 218

5.19.1 Overview ............................................................................................ 218

5.19.2 Architecture......................................................................................... 218

SMBus Controller (D31:F3) ............................................................................... 219

5.20.1 Host Controller..................................................................................... 219

5.20.1.1 Command Protocols ................................................................ 220

5.20.2 Bus Arbitration..................................................................................... 223

5.20.3 Bus Timing .......................................................................................... 224

5.20.3.1 Clock Stretching ..................................................................... 224

5.20.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 224

5.20.4 Interrupts / SMI#................................................................................. 224

5.20.5 SMBALERT# ........................................................................................ 225

5.20.6 SMBus CRC Generation and Checking...................................................... 225

5.20.7 SMBus Slave Interface .......................................................................... 226

5.20.7.1 Format of Slave Write Cycle ..................................................... 226

5.20.7.2 Format of Read Command........................................................ 228

5.20.7.3 Slave Read of RTC Time Bytes .................................................. 230

5.20.7.4 Format of Host Notify Command ............................................... 230

Thermal Management ...................................................................................... 232

5.21.1 Thermal Sensor ................................................................................... 232

5.21.1.1 Internal Thermal Sensor Operation............................................ 232

5.21.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 233

5.21.2.1 Supported Addresses............................................................... 234

5.21.2.2 I2C Write Commands to the Intel® ME ....................................... 235

5.21.2.3 Block Read Command.............................................................. 235

5.21.2.4 Read Data Format................................................................... 237

5.21.2.5 Thermal Data Update Rate ....................................................... 238

5.21.2.6 Temperature Comparator and Alert ........................................... 239

5.21.2.7 BIOS Set Up........................................................................... 240

5.21.2.8 SMBus Rules .......................................................................... 241

5.21.2.9 Case for Considerations ........................................................... 242

Intel® High Definition Audio Overview (D27:F0) .................................................. 244

Datasheet

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