BD82HM55QMNT Просмотр технического описания (PDF) - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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5.14
5.15
5.16
5.13.6.5 LPC Devices and CLKRUN# ....................................................... 172
5.13.7 Sleep States ........................................................................................ 172
5.13.7.1 Sleep State Overview............................................................... 172
5.13.7.2 Initiating Sleep State ............................................................... 172
5.13.7.3 Exiting Sleep States................................................................. 173
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message ................... 174
5.13.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 175
5.13.8 Event Input Signals and Their Usage ....................................................... 175
5.13.8.1 PWRBTN# (Power Button) ........................................................ 175
5.13.8.2 RI# (Ring Indicator) ................................................................ 177
5.13.8.3 PME# (PCI Power Management Event) ....................................... 177
5.13.8.4 SYS_RESET# Signal ................................................................ 177
5.13.8.5 THRMTRIP# Signal .................................................................. 177
5.13.9 ALT Access Mode .................................................................................. 178
5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode............. 179
5.13.9.2 PIC Reserved Bits.................................................................... 181
5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode............. 181
5.13.10System Power Supplies, Planes, and Signals............................................. 181
5.13.10.1Power Plane Control with SLP_S3#,
SLP_S4#, SLP_S5#, SLP_M# and SLP_LAN# .............................. 181
5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 182
5.13.10.3PWROK Signal ........................................................................ 182
5.13.10.4BATLOW# (Battery Low) (Mobile Only)....................................... 182
5.13.11Clock Generators .................................................................................. 182
5.13.12Legacy Power Management Theory of Operation ....................................... 183
5.13.12.1APM Power Management (Desktop Only) .................................... 183
5.13.12.2Mobile APM Power Management (Mobile Only) ............................. 183
5.13.13Reset Behavior ..................................................................................... 183
System Management (D31:F0) .......................................................................... 185
5.14.1 Theory of Operation .............................................................................. 185
5.14.1.1 Detecting a System Lockup....................................................... 185
5.14.1.2 Handling an Intruder ............................................................... 186
5.14.1.3 Detecting Improper Flash Programming...................................... 186
5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus.................... 186
5.14.2 TCO Modes .......................................................................................... 186
5.14.2.1 TCO Legacy/Compatible Mode ................................................... 186
5.14.2.2 Advanced TCO Mode ................................................................ 188
General Purpose I/O (D31:F0) ........................................................................... 189
5.15.1 Power Wells ......................................................................................... 189
5.15.2 SMI# SCI and NMI Routing .................................................................... 189
5.15.3 Triggering............................................................................................ 189
5.15.4 GPIO Registers Lockdown ...................................................................... 189
5.15.5 Serial POST Codes Over GPIO................................................................. 190
5.15.5.1 Theory of operation ................................................................. 190
5.15.5.2 Serial Message Format ............................................................. 191
SATA Host Controller (D31:F2, F5)..................................................................... 192
5.16.1 SATA Feature Support ........................................................................... 193
5.16.2 Theory of Operation .............................................................................. 194
5.16.2.1 Standard ATA Emulation........................................................... 194
5.16.2.2 48-Bit LBA Operation ............................................................... 194
5.16.3 SATA Swap Bay Support ........................................................................ 194
5.16.4 Hot Plug Operation................................................................................ 194
5.16.4.1 Low Power Device Presence Detection ........................................ 194
5.16.5 Function Level Reset Support (FLR) ......................................................... 195
5.16.5.1 FLR Steps............................................................................... 195
5.16.6 Intel® Rapid Storage Technology Configuration......................................... 195
5.16.6.1 Intel® Rapid Storage Manager RAID Option ROM ......................... 196
5.16.7 Power Management Operation ................................................................ 196
5.16.7.1 Power State Mappings.............................................................. 196
5.16.7.2 Power State Transitions............................................................ 197
5.16.7.3 SMI Trapping (APM)................................................................. 198
5.16.8 SATA Device Presence ........................................................................... 198
5.16.9 SATA LED ............................................................................................ 199
5.16.10AHCI Operation .................................................................................... 199
5.16.11SGPIO Signals ...................................................................................... 199
5.16.11.1Mechanism ............................................................................. 199
5.16.11.2Message Format...................................................................... 200
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