BD82HM55QMNT Просмотр технического описания (PDF) - Intel

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BD82HM55QMNT

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

Contents

1

Introduction ............................................................................................................ 39

1.1 About This Manual ............................................................................................. 39

1.2 Overview ......................................................................................................... 42

1.2.1 Capability Overview ................................................................................ 44

1.3 Intel® 5 Series Chipset and Intel® 3400 Series Chipset SKU Definition ..................... 50

1.4 Reference Documents ........................................................................................ 52

2

Signal Description ................................................................................................... 53

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

2.19

2.20

2.21

2.22

2.23

2.24

2.25

2.26

2.27

2.28

Direct Media Interface (DMI) to Host Controller ..................................................... 55

PCI Express* .................................................................................................... 55

Firmware Hub Interface...................................................................................... 56

PCI Interface .................................................................................................... 57

Serial ATA Interface........................................................................................... 59

LPC Interface.................................................................................................... 62

Interrupt Interface ............................................................................................ 62

USB Interface ................................................................................................... 63

Power Management Interface.............................................................................. 65

Processor Interface............................................................................................ 68

SMBus Interface................................................................................................ 68

System Management Interface............................................................................ 68

Real Time Clock Interface ................................................................................... 69

Miscellaneous Signals ........................................................................................ 70

Intel® High Definition Audio Link ......................................................................... 71

Controller Link (Mobile Only)............................................................................... 72

Serial Peripheral Interface (SPI) .......................................................................... 72

Intel® Quiet System Technology and Thermal Reporting ......................................... 73

JTAG Signals .................................................................................................... 74

Clock Signals .................................................................................................... 74

LVDS Signals (Mobile only) ................................................................................. 76

Analog Display /CRT DAC Signals ........................................................................ 77

Intel® Flexible Display Interface (FDI).................................................................. 78

Digital Display Signals........................................................................................ 79

General Purpose I/O Signals ............................................................................... 82

Manageability Signals ........................................................................................ 85

Power and Ground Signals .................................................................................. 86

Pin Straps ........................................................................................................ 88

2.28.1 Functional Straps ................................................................................... 88

2.28.2 External RTC Circuitry ............................................................................. 92

3 PCH Pin States......................................................................................................... 93

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 93

3.2 Output and I/O Signals Planes and States............................................................. 95

3.3 Power Planes for Input Signals .......................................................................... 106

4 System Clocks ....................................................................................................... 113

5 Functional Description ........................................................................................... 117

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 117

5.1.1 PCI Bus Interface ................................................................................. 117

5.1.2 PCI Bridge As an Initiator ...................................................................... 117

5.1.2.1 Memory Reads and Writes........................................................ 118

5.1.2.2 I/O Reads and Writes .............................................................. 118

5.1.2.3 Configuration Reads and Writes ................................................ 118

5.1.2.4 Locked Cycles ........................................................................ 118

5.1.2.5 Target / Master Aborts............................................................. 118

5.1.2.6 Secondary Master Latency Timer............................................... 118

5.1.2.7 Dual Address Cycle (DAC) ........................................................ 118

5.1.2.8 Memory and I/O Decode to PCI................................................. 119

5.1.3 Parity Error Detection and Generation ..................................................... 119

5.1.4 PCIRST# ............................................................................................. 120

5.1.5 Peer Cycles ......................................................................................... 120

5.1.6 PCI-to-PCI Bridge Model........................................................................ 121

5.1.7 IDSEL to Device Number Mapping .......................................................... 121

Datasheet

3

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