BD82HM55QMNT Просмотр технического описания (PDF) - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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10.1.28D29IP—Device 29 Interrupt Pin Register .................................................. 391
10.1.29D28IP—Device 28 Interrupt Pin Register .................................................. 392
10.1.30D27IP—Device 27 Interrupt Pin Register .................................................. 393
10.1.31D26IP—Device 26 Interrupt Pin Register .................................................. 394
10.1.32D25IP—Device 25 Interrupt Pin Register .................................................. 394
10.1.33D22IP—Device 22 Interrupt Pin Register .................................................. 394
10.1.34D31IR—Device 31 Interrupt Route Register .............................................. 395
10.1.35D30IR—Device 30 Interrupt Route Register .............................................. 396
10.1.36D29IR—Device 29 Interrupt Route Register .............................................. 397
10.1.37D28IR—Device 28 Interrupt Route Register .............................................. 398
10.1.38D27IR—Device 27 Interrupt Route Register .............................................. 399
10.1.39D26IR—Device 26 Interrupt Route Register .............................................. 400
10.1.40D25IR—Device 25 Interrupt Route Register .............................................. 401
10.1.41D24IR—Device 24 Interrupt Route Register .............................................. 402
10.1.42D22IR—Device 22 Interrupt Route Register .............................................. 403
10.1.43OIC—Other Interrupt Control Register ..................................................... 404
10.1.44PRSTS—Power and Reset Status ............................................................. 405
10.1.45CIR7—Chipset Initalization Register 7 ...................................................... 405
10.1.46CIR8—Chipset Initialization Register 8 ..................................................... 406
10.1.47CIR9—Chipset Initialization Register 9 ..................................................... 406
10.1.48CIR10—Chipset Initialization Register 10.................................................. 406
10.1.49CIR13—Chipset Initialization Register 13.................................................. 406
10.1.50CIR14—Chipset Initialization Register 14.................................................. 406
10.1.51CIR15—Chipset Initialization Register 15.................................................. 407
10.1.52CIR16—Chipset Initialization Register 16.................................................. 407
10.1.53CIR17—Chipset Initialization Register 17.................................................. 407
10.1.54CIR18—Chipset Initialization Register 18.................................................. 407
10.1.55CIR19—Chipset Initialization Register 19.................................................. 407
10.1.56CIR20—Chipset Initialization Register 20.................................................. 408
10.1.57CIR21—Chipset Initialization Register 21.................................................. 408
10.1.58CIR22—Chipset Initialization Register 22.................................................. 408
10.1.59RC—RTC Configuration Register .............................................................. 409
10.1.60HPTC—High Precision Timer Configuration Register ................................... 409
10.1.61GCS—General Control and Status Register ............................................... 410
10.1.62BUC—Backed Up Control Register ........................................................... 412
10.1.63FD—Function Disable Register ................................................................ 413
10.1.64CG—Clock Gating.................................................................................. 415
10.1.65FDSW—Function Disable SUS Well .......................................................... 416
10.1.66FD2—Function Disable 2 ........................................................................ 416
10.1.67MISCCTL—Miscellaneous Control Register ................................................ 417
10.1.68USBOCM1 - Overcurrent MAP Register 1 .................................................. 418
10.1.69USBOCM2 - Overcurrent MAP Register 2 .................................................. 419
10.1.70RMHWKCTL- Rate Matching Hub Wake Control Register ............................. 420
11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 423
11.1 PCI Configuration Registers (D30:F0) ................................................................. 423
11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)............................. 424
11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 424
11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) ............................................. 424
11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0) .......................................... 425
11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0) ............................ 427
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)............................................. 427
11.1.7 PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)................................................................................ 428
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 428
11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................... 428
11.1.10SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)................................................................................ 429
11.1.11IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)................................................................................ 429
11.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................ 430
11.1.13MEMBASE_LIMIT—Memory Base and Limit Register
(PCI-PCI—D30:F0)................................................................................ 431
11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) ..................................................... 431
11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................... 432
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