T2080 Просмотр технического описания (PDF) - Freescale Semiconductor

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T2080

T2080 Product Brief Also supports T2081

Freescale Semiconductor 

Chip features

• 2x, and 4x LP-serial link interfaces, with transmission rates of 2.5, 3.125, or 5.0 Gbaud (data rates of 1.0, 2.0, 2.5, or

4.0 Gbps) per lane

• Auto-detection of 1x, 2x, or 4x mode operation during port initialization

• 34-bit addressing and up to 256-byte data payload

• Support for SWRITE, NWRITE, NWRITE_R and Atomic transactions

• Receiver-controlled flow control

• RapidIO error injection

• Internal LP-serial and application interface-level loopback modes

The Serial RapidIO controller also supports the following capabilities, many of which are leveraged by the RMan to efficient

chip-to-chip communication through the DPAA:

• Support for RapidIO Interconnect Specification 2.1, "Part 2: Message Passing Logical Specification"

• Supports RapidIO Interconnect Specification 2.1, "Part 10: Data Streaming Logical Specification"

• Supports RapidIO Interconnect Specification 2.1, "Annex 2: Session Management Protocol"

• Supports basic stream management flow control (XON/XOFF) using extended header message format

• Up to 16 concurrent inbound reassembly operations

• One additional reassembly context is reservable to a specific transaction type

• Support for outbound Type 11 messaging

• Support for outbound Type 5 NWRITE and Type 6 SWRITE transactions

• Support for inbound Type 11 messaging

• Support for inbound Type 9 data streaming transactions

• Support for outbound Type 9 data streaming transactions

• Up to 64 KB total payload

• Support for inbound Type 10 doorbell transactions

• Transaction steering through doorbell header classification

• Support for outbound Type 10 doorbell transactions

• Ordering can be maintained with respect to other types of traffic.

• Support for inbound and outbound port-write transactions

• Data payloads of 4 to 64 bytes

4.9.3 SATA

Each of the SoC's two SATA controllers is compliant with the Serial ATA 2.6 Specification. Each of the SATA controllers

has the following features:

• Supports speeds: 1.5 Gbps (first-generation SATA), and 3Gbps (second-generation SATA )

• Supports advanced technology attachment packet interface (ATAPI) devices

• Contains high-speed descriptor-based DMA controller

• Supports native command queuing (NCQ) commands

• Supports port multiplier operation

• Supports hot plug including asynchronous signal recovery

4.10 Data Path Acceleration Architecture (DPAA)

This chip includes an enhanced implementation of the QorIQ Datapath Acceleration Architecture (DPAA). This architecture

provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPUs. These

resources are abstracted as enqueue/dequeue operations by CPU 'portals' into the datapath. Beyond enabling multicore

sharing of resources, the DPAA significantly reduces software overheads associated with high-touch packet-processing

operations.

Examples of the types of packet-processing services that this architecture is optimized to support are as follows:

T2080 Product Brief, Rev 0, 04/2014

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Freescale Semiconductor, Inc.

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