BD82B65 Просмотр технического описания (PDF) - Intel
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BD82B65 Datasheet PDF : 934 Pages
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10.1.29
10.1.30
10.1.31
10.1.32
10.1.33
10.1.34
10.1.35
10.1.36
10.1.37
10.1.38
10.1.39
10.1.40
10.1.41
10.1.42
10.1.43
10.1.44
10.1.45
10.1.46
10.1.47
10.1.48
10.1.49
10.1.50
10.1.51
10.1.52
10.1.53
D29IR—Device 29 Interrupt Route Register........................................... 393
D28IR—Device 28 Interrupt Route Register........................................... 394
D27IR—Device 27 Interrupt Route Register........................................... 395
D26IR—Device 26 Interrupt Route Register........................................... 396
D25IR—Device 25 Interrupt Route Register........................................... 397
D22IR—Device 22 Interrupt Route Register........................................... 398
OIC—Other Interrupt Control Register .................................................. 399
PRSTS—Power and Reset Status Register ............................................. 400
PM_CFG—Power Management Configuration Register ............................. 401
DEEP_S4_POL—Deep S4/S5 From S4 Power Policies
Register ........................................................................................... 402
DEEP_S5_POL—Deep S4/S5 From S5 Power Policies
Register ........................................................................................... 402
PMSYNC_CFG—PMSYNC Configuration Register ..................................... 403
RC—RTC Configuration Register .......................................................... 404
HPTC—High Precision Timer Configuration Register ................................ 404
GCS—General Control and Status Register ............................................ 405
BUC—Backed Up Control Register ........................................................ 407
FD—Function Disable Register ............................................................. 407
CG—Clock Gating Register .................................................................. 409
FDSW—Function Disable SUS Well Register........................................... 410
DISPBDF—Display Bus, Device and Function
Initialization Register ......................................................................... 411
FD2—Function Disable 2 Register ........................................................ 411
MISCCTL—Miscellaneous Control Register ............................................. 412
USBOCM1—Overcurrent MAP Register 1 ............................................... 413
USBOCM2—Overcurrent MAP Register 2 ............................................... 414
RMHWKCTL—Rate Matching Hub Wake Control Register.......................... 415
11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 417
11.1 PCI Configuration Registers (D30:F0) ................................................................. 417
11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ......................... 418
11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0).......................... 418
11.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0).......................................... 418
11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)....................................... 419
11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0) ........................ 421
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ......................................... 421
11.1.7 PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0) ............................................................................ 422
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .............................. 422
11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ................................... 422
11.1.10 SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0) ............................................................................ 423
11.1.11 IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0) ............................................................................ 423
11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ......................... 424
11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register
(PCI-PCI—D30:F0) ............................................................................ 425
11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) .................................................. 425
11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................ 426
11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................ 426
11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) ....................... 426
11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)........................ 426
11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ............................... 427
11.1.20 SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0) ............................................................................ 428
11.1.21 DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0) ............................................................................ 429
11.1.22 BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0) ............................................................................ 430
11.1.23 BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0) ............................................................................ 431
11.1.24 SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0) ............................................................................ 432
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