TEA2164S Просмотр технического описания (PDF) - STMicroelectronics
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TEA2164S Datasheet PDF : 16 Pages
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TEA2164S
BLOCK DIAGRAM
R1
9
tON
LIMITATION
C1
10
VLF
OSCILLATOR
Valid
Soft
Start
IC(Max.)
11
V-
12 13
IC(Max.)
DETECTION
IC(M3)
IC(M2)
IC(M1)
1
Sawtooth
Return
RS
Q
13%
OUT V+
VCC
14
15
16
VCC
MONITORING
VCC 16V
Internal
VCC
TEA2164S
1
&
SQ
IC COPY
V+
+
AMP
-
&
1
RQ
DELAY
AMP
Sawtooth
Return
RC
OSCILLATOR
&
SYNC
Positive
Pulse
Negative Pulse
SYNC
SWITCH
PULSE
SHAPER
8
7
6
COSC ROSC
IN
Figure 1 : Simplified Application Diagram
V-
VCC < 4.6V
R
Q
S
REPETITIVE
OVERCURRENT
PROTECTION
54
V-
3
2
1
C2
ICOPY
GND
VCC
IN TEA2164S OUT
SLAVE I.C.
VOUT
TEA5170
VREF
MASTER I.C.
PWM
SYNC.
INPUT
2/16
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