MPC8270VRI Просмотр технического описания (PDF) - Freescale Semiconductor

Номер в каталоге

Компоненты Описание

производитель

MPC8270VRI

PowerQUICC II Family Hardware Specifications

Freescale Semiconductor 

Overview

— Includes all of the configuration registers (which are automatically loaded from the EPROM

and used to configure the MPC8280) required by the PCI standard as well as message and

doorbell registers

— Supports the I2O standard

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August

3, 1998)

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

— Uses the local bus signals, removing need for additional pins

• System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

• 12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other

user-definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

• CPU core can be disabled and the device can be used in slave mode to an external core

• Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications protocols

— Interfaces to G2_LE core through an on-chip 32 KB dual-port data RAM, an on-chip 32 KB

dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII) or reduced media independent interface (RMII)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

5

Share Link: