MPC8270VVB Просмотр технического описания (PDF) - Freescale Semiconductor
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MPC8270VVB Datasheet PDF : 83 Pages
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Clock Configuration Modes
Table 16. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
Input hold times
Boundary-scan data tJTDXKH
10
—
ns
4, 7
TMS, TDI
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data tJTKLDV
—
10
ns
5, 7
TDO
tJTKLOV
—
10
ns
5. 7
Output hold times
Boundary-scan data tJTKLDX
1
TDO
tJTKLOX
1
—
ns
5, 7
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data tJTKLDZ
1
TDO
tJTKLOZ
1
10
ns
5, 6
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to tTCLK.
5 Non-JTAG signal output timing with respect to tTCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
7 Clock Configuration Modes
This SoC includes the following clocking modes:
• Local
• PCI host
• PCI agent
The clocking mode is set according to the following input pins as shown in the following table:
• PCI_MODE
• PCI_CFG[0]
• PCI_MODCK
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
26
Freescale Semiconductor
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