MPC8270VVB Просмотр технического описания (PDF) - Freescale Semiconductor

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MPC8270VVB

PowerQUICC II Family Hardware Specifications

Freescale Semiconductor 

AC Electrical Characteristics

This figure shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

CLKin

DATA bus, ECC, and PARITY mode

input signals

Pipeline mode—

DATA bus, ECC, and PARITY mode

input signals

DP mode input signal

Pipeline mode—

DP mode input signal

DP mode output signal

sp33b

sp13

sp13a

sp14

sp14a

sp10

sp10

sp10

sp10

sp30

Figure 10. Parity Mode Diagram

This figure shows signal behavior in MEMC mode.

CLKin

V_CLK

Memory controller signals

sp34/sp30

Figure 11. MEMC Mode Diagram

NOTE

Generally, all SoC bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however,

trigger on four points within a CLKin cycle. Each cycle is divided by four

internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and

T3 at the falling edge, of CLKin. However, the spacing of T2 and T4

depends on the PLL clock ratio selected, as shown in Table 15.

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

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Freescale Semiconductor

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