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SC16IS740

Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors. 

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[4] HVQFN24 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

7. Functional description

The UART will perform serial-to-I2C conversion on data characters received from

peripheral devices or modems, and I2C-to-serial conversion on data characters

transmitted by the host. The complete status the SC16IS740/750/760 UART can be read

at any time during functional operation by the host.

The SC16IS740/750/760 can be placed in an alternate mode (FIFO mode) relieving the

host of excessive software overhead by buffering received/transmitted characters. Both

the receiver and transmitter FIFOs can store up to 64 characters (including three

additional bits of error status per character for the receiver FIFO) and have selectable or

programmable trigger levels.

The SC16IS740/750/760 has selectable hardware flow control and software flow control.

Hardware flow control significantly reduces software overhead and increases system

efficiency by automatically controlling serial data flow using the RTS output and CTS input

signals. Software flow control automatically controls data flow by using programmable

Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216 – 1).

7.1 Trigger levels

The SC16IS740/750/760 provides independently selectable and programmable trigger

levels for both receiver and transmitter interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one character. The selectable trigger levels are available via the FCR. The programmable

trigger levels are available via the TLR. If TLR bits are cleared then selectable trigger level

in FCR is used. If TLR bits are not cleared then programmable trigger level in TLR is used.

7.2 Hardware flow control

Hardware flow control is comprised of auto CTS and auto RTS (see Figure 8). Auto CTS

and auto RTS can be enabled/disabled independently by programming EFR[7:6].

With auto CTS, CTS must be active before the UART can transmit data.

Auto RTS only activates the RTS output when there is enough room in the FIFO to receive

data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and

resume trigger levels in the TCR determine the levels at which RTS is

activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are

used in place of TCR.

If both auto CTS and auto RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware flow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

SC16IS740_750_760

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 9 June 2011

© NXP B.V. 2011. All rights reserved.

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