SCC68681 Просмотр технического описания (PDF) - NXP Semiconductors.

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SCC68681

Dual asynchronous receiver/transmitter (DUART)

NXP Semiconductors. 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product data

SCC68681

Table 2. Register Bit Formats

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR1A

MR1B

RxRTS

CONTROL

0 = No

1 = Yes

RxINT

SELECT

0 = RxRDY

1 = FFULL

ERROR

MODE*

0 = Char

1 = Block

PARITY MODE

00 = With Parity

01 = Force Parity

10 = No Parity

11 = Multidrop Mode**

PARITY

TYPE

0 = Even

1 = Odd

BITS PER

CHARACTER

00 = 5

01 = 6

10 = 7

11 = 8

NOTE:

* In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.

** Please see Receiver Reset note on page 19.

BIT 7

BIT 6

BIT 5

BIT 4

MR2A

MR2B

CHANNEL MODE

00 = Normal

01 = Auto-Echo

10 = Local loop

11 = Remote loop

TxRTS

CONTROL

0 = No

1 = Yes

CTS

ENABLE Tx

0 = No

1 = Yes

NOTE:

*Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.

BIT 3

0 = 0.563

1 = 0.625

2 = 0.688

3 = 0.750

BIT 2

BIT 1

STOP BIT LENGTH*

4 = 0.813

5 = 0.875

6 = 0.938

7 = 1.000

8 = 1.563

9 = 1.625

A = 1.688

B = 1.750

BIT 0

C = 1.813

D = 1.875

E = 1.938

F = 2.000

CSRA

CSRB

BIT 7

BIT 6

BIT 5

RECEIVER CLOCK SELECT

See Text

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TRANSMITTER CLOCK SELECT

See Text

NOTE:

* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,

SCC68681 and SCC2698B” in application notes elsewhere in this publication

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CRA

CRB

Not used –

must be 0

MISCELLANEOUS COMMANDS

See Text

DISABLE Tx

0 = No

1 = Yes

ENABLE Tx

0 = No

1 = Yes

DISABLE Rx

0 = No

1 = Yes

ENABLE Rx

0 = No

1 = Yes

NOTE:

*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot

be loaded. For Rx and Tx performing a Disable and Enable at the same time results in Disable.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SRA

SRB

RECEIVED

BREAK*

0 = No

1 = Yes

FRAMING

ERROR*

0 = No

1 = Yes

PARITY

ERROR*

0 = No

1 = Yes

OVERRUN

ERROR

0 = No

1 = Yes

TxEMT

0 = No

1 = Yes

TxRDY

0 = No

1 = Yes

FFULL

0 = No

1 = Yes

RxRDY

0 = No

1 = Yes

NOTE:

*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the

top of the FIFO together with bits (4:0). These bits are cleared by a ‘reset error status’ command. In character mode they are discarded when

the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error reset

command (command 4x) or a receiver reset.

OPCR

BIT 7

OP7

BIT 6

OP6

BIT 5

OP5

BIT 4

OP4

0 = OPR[7]

1 = TxRDYB

0 = OPR[6]

1 = TxRDYA

0 = OPR[5]

1 = RxRDY/

FFULLB

0 = OPR[4]

1 = RxRDY/

FFULLA

BIT 3

BIT 2

OP3

00 = OPR[3]

01 = C/T OUTPUT

10 = TxCB(1×)

11 = RxCB(1×)

BIT 1

BIT 0

OP2

00 = OPR[2]

01 = TxCA(16×)

10 = TxCA(1×)

11 = RxCA(1×)

OPR

BIT 7

BIT 6

BIT 5

BIT 4

OPR bit 0

1

0

1

0

1

0

1

OP pin 1

0

1

0

1

0

1

0

NOTE:

The level at the OP pin is the inverse of the bit in the OPR register.

BIT 3

0

1

1

0

BIT 2

0

1

1

0

BIT 1

0

1

1

0

BIT 0

0

1

1

0

2004 Apr 06

9

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