USB3318C-CP-TR Просмотр технического описания (PDF) - Microchip Technology
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USB3318C-CP-TR
Microchip Technology
USB3318C-CP-TR Datasheet PDF : 73 Pages
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Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 13MHz Reference Clock
Datasheet
Table 2.1 USB3318 Pin Description (continued)
PIN
DIRECTION/ ACTIVE
NAME
TYPE
LEVEL
DESCRIPTION
4
VDD3.3
Power
N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3318.
5
DM
I/O,
N/A D- pin of the USB cable.
Analog
6
DP
I/O,
N/A D+ pin of the USB cable.
Analog
7
CPEN
Output,
High External 5 volt supply enable. This pin is
CMOS
used to enable the external Vbus power
supply. The CPEN pin is low on POR.
This pad uses VDD3.3 logic level.
8
DATA[7]
I/O,
N/A ULPI bi-directional data bus. DATA[7] is
CMOS
the MSB.
9
DATA[6]
I/O,
N/A ULPI bi-directional data bus.
CMOS
10
DATA[5
I/O,
N/A ULPI bi-directional data bus.
CMOS
11
DATA[4]
I/O,
N/A ULPI bi-directional data bus.
CMOS
12
CLKOUT
Output,
N/A 60MHz reference clock output. All ULPI
CMOS
signals are driven synchronous to the
rising edge of this clock.
Following POR or hardware reset, the
voltage at CLKOUT must not exceed
VIH_ED as provided in Table 4.4.
13
DATA[3]
I/O,
N/A ULPI bi-directional data bus.
CMOS
14
DATA[2]
I/O,
N/A ULPI bi-directional data bus.
CMOS
15
DATA[1]
I/O,
N/A ULPI bi-directional data bus.
CMOS
16
DATA[0]
I/O,
N/A ULPI bi-directional data bus. DATA[0] is
CMOS
the LSB.
17
VDDIO
Power
N/A 1.8V to 3.3V ULPI interface supply
voltage. This voltage sets the value of
VOH for the ULPI interface.
18
NXT
Output,
High The PHY asserts NXT to throttle the data.
CMOS
When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Revision 2.1 (06-02-10)
10
DATASHEET
SMSC USB3318 REV C
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