ATSAMA5D41A-CU Просмотр технического описания (PDF) - Atmel Corporation
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ATSAMA5D41A-CU Datasheet PDF : 1808 Pages
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1. Block Diagram
Figure 1-1. Block Diagram
TST
XIN
XOUT
PCK0–PCK2
FIQ
IRQ
DRXD
DTXD
VDDCORE
NRST
VDDBU
XIN32
XOUT32
SHDN
WKUP
PLLA PLLUTMI
12 MHz Osc
12 MHz RC Osc
WDT
PMC
PIT
SAIC
AIC
DBGU
POR
Fuse Box
RSTC
POR
Backup
Area
32.768 kHz
Crystal Osc
64 KHz RC
SHDWC
RTC
PIO
JTAG / SWD
HS HS
Trans Trans
HS
Trans
In-Circuit Emulator
Trust
NEON
Zone Cortex-A5 FPU
32 KB
32 KB
ICache MMU DCache
PC PB PA
HS EHCI
USB HOST
HS USB
Device
DMA
DMA
128 KB L2 Cache
GMAC0
GMAC1
10/100
DMA
PIO
Video
Decoder
DMA
LCD
DMA
I/D
ISI
DMA
Trustzone Secured Multi-Layer Matrix
ROM
128 KB
SRAM
128 KB
16-ch.
DMA0
TRNG CPKCC
SHA
AES
TDES
ICM
(SHA)
Peripheral Peripheral
Bridge 0 Bridge 1
16-ch.
DMA1
DDR2
LPDDR
LPDDR2
512 MB
Scrambling
Secured EBI
NAND Flash
Controller
MCL/SLC
ECC
(4 KB SRAM)
Scrambling
Reduced
Static
Memory
Controller
Scrambling
PIOBU[7..0]
SECURAM
8 KB
+
512 bits
SMD
4-ch. TC0
PWM TC1
TC2
TWI0
TWI1
TWI2
TWI3
USART0
USART1
USART2
USART3
USART4
UART0
UART1
SPI0
SPI1
SPI2
SSC0
SSC1
MCI0/MCI1
SD/SDIO
eMMC
5-ch.
10-bit ADC
Touchscreen
PIO PIO
PIO
DDR_A0–DDR_A13
DDR_D0–DDR_D31
DDR_DQM[3..0]
DDR_DQS[3..0]
DDR_DQSN[3..0]
DDR_CS
DDR_CLK, DDR_CLKN
DDR_CKE
DDR_RAS, DDR_CAS
DDR_WE
DDR_BA[2..0]
D0–D15
A21/NANDALE
A22/NANDCLE
NRD/NANDOE
NWE/NWR0/NANDWE
NCS3/NANDCS
NANDRDY
A0/NBS0
A1–A20
A23–A25
NWR1/NBS1
NCS0, NCS1, NCS2
NWAIT
SPI0_,
SPI1_,
SPI2_
Key
Trustzone Access Right Management
xxx Always Secured
xxx Programmable Secured
xxx Secured and Non-Secured
xxx Always Non-Secured
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