AT90PWM81(2010) Просмотр технического описания (PDF) - Atmel Corporation

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AT90PWM81
(Rev.:2010)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refer-

ence. This will in many cases remove the need for using the dedicated compare instructions, resulting in

faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when

returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value 0

0

0

0

0

0

0

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt enable con-

trol is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none

of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by

hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent inter-

rupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for

the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and

a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD

arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow

Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set

Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Descrip-

tion” for detailed information.

10 AT90PWM81

7734P–AVR–08/10

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