24C128 Просмотр технического описания (PDF) - ON Semiconductor
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24C128 Datasheet PDF : 16 Pages
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CAT24C128
Table 7. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 10)
Standard
VCC = 1.8 V − 5.5 V
Fast
VCC = 1.8 V − 5.5 V
Fast−Plus (Note 13)
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Symbol
Parameter
Min
Max
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
1,000
tHD:STA
START Condition Hold Time
4
0.6
0.25
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
tHIGH
High Period of SCL Clock
4
0.6
0.40
tSU:STA
START Condition Setup Time
4.7
0.6
0.25
tHD:DAT
Data In Hold Time
0
0
0
tSU:DAT
Data In Setup Time
250
100
50
tR (Note 11)
SDA and SCL Rise Time
1,000
300
100
tF (Note 11)
SDA and SCL Fall Time
300
300
100
tSU:STO
STOP Condition Setup Time
4
0.6
0.25
tBUF
Bus Free Time Between
4.7
1.3
0.5
STOP and START
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
tAA
SCL Low to Data Out Valid
3.5
0.9
0.40
ms
tDH
Data Out Hold Time
100
100
50
ns
Ti (Note 11)
Noise Pulse Filtered at SCL
100
100
and SDA Inputs
50
ns
tSU:WP
tHD:WP
tWR
tPU
(Notes 11, 12)
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
0
2.5
5
1
0
ms
1
ms
5
ms
0.1
1
ms
10. Test conditions according to “A.C. Test Conditions” table.
11. Tested initially and after a design or process change that affects this parameter.
12. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
13. Fast−Plus (1 MHz) speed class available for new product revision “C”. The die revision “C” is identified by letter “C” or a dedicated marking
code on top of the package.
Table 8. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x VCC to 0.8 x VCC
v 50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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