ADP3212(OLD) Просмотр технического описания (PDF) - ON Semiconductor

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ADP3212
(Rev.:OLD)

7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller

ON Semiconductor 

ADP3212/NCP3218

SPECIFICATIONS

VCC = PVCC = 5V, FBRTN = PGND = GND = 0 V, H = 5V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC =

1.2000 V, TA = −40°C to 100°C, unless otherwise noted.1 Current entering a pin (sink current) has a positive sign.

Table 1.

Parameter

VOLTAGE CONTROL

VOLTAGE ERROR AMPLIFIER

(VEAMP)

FB, LLINE Voltage Range2

FB, LLINE Offset Voltage2

LLINE Bias Current

FB Bias Current

LLINE Positioning Accuracy

COMP Voltage Range2

COMP Current

COMP Slew Rate

Symbol

VFB, VLLINE

VOSVEA

ILLINE

IFB

VFB − VVID

VCOMP

ICOMP

SRCOMP

Gain Bandwidth2

GBW

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range2

VDAC Accuracy

VFB − VVID

VDAC Differential

Nonlinearity2

VDAC Line Regulation

VDAC Boot Voltage

Soft-start Delay2

Soft-start Time

Boot Delay

VDAC Slew Rate2

ΔVFB

VBOOTFB

tDSS

tSS

tBOOT

FBRTN Current

VOLTAGE MONITORING

and PROTECTION

POWER GOOD

CSREF Under-voltage

Threshold

CSREF Over-voltage

Threshold

IFBRTN

VUVCSREF

VOVCSREF

Conditions

Min Typ Max Units

Relative to CSREF = VDAC

Relative to CSREF = VDAC

Measured on FB relative to VVID, LLINE forced 80 mV

below CSREF

COMP = 2 V, CSREF = VDAC

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

CCOMP = 10 pF, CSREF = VDAC, Open loop

configuration

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

Non-inverting unit gain configuration, RFB = 1

kOhm

−200

−0.5

−100

−1

−77.5 −80

+200 mV

+0.5 mV

+100 nA

+1 μA

−82.5 mV

0.85

4.0 V

−0.75

mA

6

mA

15

V/μs

-20

V/μs

20

MHz

See VID table

0

Measured on FB (includes offset), relative to VVID

VVID = 1.2000 V to 1.5000 V, T = −40C to 100C

−8.5

VVID = 0.3000 V to 1.1875 V, T = −40C to 100C

−7.5

−1

1.5 V

+8.5 mV

+7.5 mV

+1 LSB

VCC = 4.75 V to 5.25 V

Measured during boot delay period

Measured from EN pos edge to FB = 50 mV

Measured from FB = 50 mV to FB settles to 1.1 V

within 5 %

Measured from FB settling to 1.1 V within 5% to

CLKEN# neg edge

Soft-start

Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit

Non-LSB VID step, DPRSLP = L, Fast C4 Exit

LSB VID step, DVID transition

0.02

%

1.100

V

200

μs

1.4

ms

60

μs

0.0625

0.25

1

0.4

−90

−200

LSB/μs

LSB/μs

LSB/μs

LSB/μs

μA

Relative to nominal VDAC voltage

Relative to nominal VDAC voltage

−240 −300

150 200

−360 mV

250 mV

Rev. SpA | Page 4 of 43

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