EL7585AILZ(2005) Просмотр технического описания (PDF) - Intersil

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производитель

EL7585AILZ
(Rev.:2005)

TFT-LCD Power Supply

Intersil 

EL7585A

there is a fault condition on CDLY or VREF. If a fault is

detected, the outputs and the input protection will turn off,

but VREF will stay on. If no fault is found, CCDLY continues

ramping up and down.

During the second ramp, the device checks the status of

VREF and over temperature. At the peak of the second ramp,

PG output goes low and enables the input protection PMOS

Q1. Q1 is a controlled FET used to prevent in-rush current into

VBOOST before VBOOST is enabled internally. Its rate of turn

on is controlled by Co. When a fault is detected, M1 will turn

off and disconnect the inductor from VIN.

With the input protection FET on, NODE1 (See Typical

Application Diagram) will rise to ~VIN. Initially the boost is not

enabled so VBOOST rises to VIN-VDIODE through the output

diode. Hence, there is a step at VBOOST during this part of the

start-up sequence. If this step is not desirable, an external

PMOS FET can be used to delay the output until the boost is

enabled internally. The delayed output appears at AVDD.

For EL7585A, VBOOST soft-start at the beginning of the third

ramp. The soft-start ramp depends on the value of the CDLY

capacitor. For CDLY of 220nF, the soft-start time is ~2ms.

VOFF turns on at the start of the fourth peak. At the fifth

peak, DELB gate goes low to turn on the external PMOS Q4

to generate a delayed VBOOST output.

VON is enabled at the beginning of the sixth ramp. AVDD,

PG, VOFF, DELB and VON are checked at end of this ramp.

Fault Protection

During the startup sequence, prior to BOOST soft-start,

VREF is checked to be within ±20% of its final value and the

device temperature is checked. If either of these are not

within the expected range, the part is disabled until the

power is recycled or EN is toggled.

If CDELAY is shorted low, then the sequence will not start,

while if CDELAY is shorted H, the first down ramp will not

occur and the sequence will not complete.

Once the start-up sequence is completed, the chip

continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF,

FBB and PG and checks for faults. During this time, the

voltage on the CDLY capacitor remains at 1.15V until either a

fault is detected, or the EN pin is pulled low.

A fault on CDELAY, VREF or temperature will shut down the

chip immediately. If a fault on any other output is detected,

CDELAY will ramp up linearly with a 5µA (typical) current to

the upper fault threshold (typically 2.4V), at which point the

chip is disabled until the power is recycled or EN is toggled.

If the fault condition is removed prior to the end of the ramp,

the voltage on the CDLY capacitor returns to 1.15V.

Typical fault thresholds for FBP, FBL, FBN and FBB are

included in the tables. PG and DELB fault thresholds are

typically 0.6V.

CINT has an internal current-limited clamp to keep the

voltage within its normal range. If CINT is shorted low, the

boost regulator will attempt to regulate to 0V. If CINT is

shorted H, the regulator switches to P mode.

If any of the regulated outputs (VBOOST, VON, VOFF or

VLOGIC) are driven above their target levels the drive

circuitry will switch off until the output returns to its expected

value.

If VBOOST is excessively loaded, the current limit will

prevent damage to the chip. While in current limit, the part

acts like a current source and the regulated output will drop.

If the output drops below the fault threshold, a ramp will be

initiated on CDELAY and, provided that the fault is sustained,

the chip will be disabled on completion of the ramp.

In some circumstances, (depending on ambient temperature

and thermal design of the board), continuous operation at

current limit may result in the over-temperature threshold

being exceeded, which will cause the part to disable

immediately.

All I/O also have ESD protection, which in many cases will

also provide overvoltage protection, relative to either ground

or VDD. However, these will not generally operate unless

abs max ratings are exceeded.

Component Selection for Start-Up Sequencing and

Fault Protection

The CREF capacitor is typically set at 220nF and is required

to stabilize the VREF output. The range of CREF is from

22nF to 1µF and should not be more than five times the

capacitor on CDEL to ensure correct start-up operation.

The CDEL capacitor is typically 220nF and has a usable

range from 47nF minimum to several microfarads - only

limited by the leakage in the capacitor reaching µA levels.

CDEL should be at least 1/5 of the value of CREF (See

above). Note with 220nF on CDEL the fault time-out will be

typically 50ms and the use of a larger/smaller value will vary

this time proportionally (e.g. 1µF will give a fault time-out

period of typically 230ms).

Fault Sequencing

The EL7585A has an advanced fault detection system which

protects the IC from both adjacent pin shorts during

operation and shorts on the output supplies.

A high quality layout/design of the PCB, in respect of

grounding quality and decoupling is necessary to avoid

falsely triggering the fault detection scheme - especially

during start-up. The user is directed to the layout guidelines

and component selection sections to avoid problems during

initial evaluation and prototype PCB generation.

14

FN7523.2

September 21, 2005

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