MCF5272VF66J Просмотр технического описания (PDF) - Freescale Semiconductor
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MCF5272VF66J Datasheet PDF : 544 Pages
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Table of Contents (Continued)
Paragraph
Number
Title
Page
Number
Chapter 9
SDRAM Controller
9.1 Overview ........................................................................................................................................ 9-1
9.2 SDRAM Controller Signals ........................................................................................................... 9-1
9.3 Interface to SDRAM Devices ........................................................................................................ 9-4
9.4 SDRAM Banks, Page Hits, and Page Misses ................................................................................ 9-6
9.5 SDRAM Registers ......................................................................................................................... 9-6
9.5.1 SDRAM Configuration Register (SDCR) .......................................................................... 9-6
9.5.2 SDRAM Timing Register (SDTR) ..................................................................................... 9-8
9.6 Auto Initialization .......................................................................................................................... 9-9
9.7 Power-Down and Self-Refresh ...................................................................................................... 9-9
9.8 Performance ................................................................................................................................. 9-10
9.9 Solving Timing Issues with SDCR[INV] .................................................................................... 9-12
9.10 SDRAM Interface ...................................................................................................................... 9-14
9.10.1 SDRAM Read Accesses ................................................................................................. 9-15
9.10.2 SDRAM Write Accesses ................................................................................................ 9-18
9.10.3 SDRAM Refresh Timing ................................................................................................ 9-20
Chapter 10
DMA Controller
10.1 DMA Data Transfer Types ......................................................................................................... 10-1
10.2 DMA Address Modes ................................................................................................................ 10-2
10.3 DMA Controller Registers ......................................................................................................... 10-2
10.3.1 DMA Mode Register (DMR) ......................................................................................... 10-2
10.3.2 DMA Interrupt Register (DIR) ....................................................................................... 10-4
10.3.3 DMA Source Address Register (DSAR) ........................................................................ 10-5
10.3.4 DMA Destination Address Register (DDAR) ................................................................ 10-6
10.3.5 DMA Byte Count Register (DBCR) ............................................................................... 10-6
Chapter 11
Ethernet Module
11.1 Overview .................................................................................................................................... 11-1
11.1.1 Features ........................................................................................................................... 11-1
11.2 Module Operation ...................................................................................................................... 11-1
11.3 Transceiver Connection ............................................................................................................. 11-3
11.4 FEC Frame Transmission ........................................................................................................... 11-4
11.4.1 FEC Frame Reception .................................................................................................... 11-5
11.4.2 CAM Interface ................................................................................................................ 11-6
11.4.3 Ethernet Address Recognition ........................................................................................ 11-6
11.4.4 Hash Table Algorithm ..................................................................................................... 11-8
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
xviii
Freescale Semiconductor
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