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MCF5272VF66J

ColdFire® Integrated Microprocessor

Freescale Semiconductor 

Table of Contents (Continued)

Paragraph

Number

Title

Page

Number

5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR) ............................................................ 5-12

5.4.6 Program Counter Breakpoint/Mask Registers

(PBR, PBMR) ............................................................................................................................ 5-13

5.4.7 Trigger Definition Register (TDR) ................................................................................... 5-14

5.5 Background Debug Mode (BDM) ............................................................................................... 5-15

5.5.1 CPU Halt .......................................................................................................................... 5-16

5.5.2 BDM Serial Interface ....................................................................................................... 5-17

5.5.2.1 Receive Packet Format ....................................................................................... 5-18

5.5.2.2 Transmit Packet Format ...................................................................................... 5-18

5.5.3 BDM Command Set ......................................................................................................... 5-19

5.5.3.1 ColdFire BDM Command Format ...................................................................... 5-20

5.5.3.1.1 Extension Words as Required .................................................................... 5-20

5.5.3.2 Command Sequence Diagrams ........................................................................... 5-21

5.5.3.3 Command Set Descriptions ................................................................................ 5-22

5.5.3.3.1 Read A/D Register (RAREG/RDREG)........................................................... 5-22

5.5.3.3.2 Write A/D Register (WAREG/WDREG) ........................................................ 5-23

5.5.3.3.3 Read Memory Location (READ) ................................................................. 5-24

5.5.3.3.4 Write Memory Location (WRITE)............................................................... 5-25

5.5.3.3.5 Dump Memory Block (DUMP) ................................................................... 5-27

5.5.3.3.6 Fill Memory Block (FILL) .......................................................................... 5-28

5.5.3.3.7 Resume Execution (GO) ............................................................................. 5-29

5.5.3.3.8 No Operation (NOP).................................................................................... 5-30

5.5.3.3.9 Read Control Register (RCREG).................................................................. 5-30

5.5.3.3.10 Write Control Register (WCREG).............................................................. 5-31

5.5.3.3.11 Read Debug Module Register (RDMREG)................................................. 5-32

5.5.3.3.12 Write Debug Module Register (WDMREG)............................................... 5-33

5.6 Real-Time Debug Support ........................................................................................................... 5-33

5.6.1 Theory of Operation .......................................................................................................... 5-34

5.6.1.1 Emulator Mode ................................................................................................... 5-35

5.6.2 Concurrent BDM and Processor Operation ...................................................................... 5-35

5.7 Processor Status, DDATA Definition ........................................................................................... 5-36

5.7.1 User Instruction Set .......................................................................................................... 5-36

5.7.2 Supervisor Instruction Set ................................................................................................ 5-40

5.8 Freescale-Recommended BDM Pinout ....................................................................................... 5-41

Chapter 6

System Integration Module (SIM)

6.1 Features .......................................................................................................................................... 6-1

6.2 Programming Model ...................................................................................................................... 6-2

6.2.1 SIM Register Memory Map ................................................................................................ 6-2

6.2.2 Module Base Address Register (MBAR) ........................................................................... 6-3

MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3

xvi

Freescale Semiconductor

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