DF8064101211300SR0VY Просмотр технического описания (PDF) - Intel

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DF8064101211300SR0VY

Intel® Atom™ Processor D2000 and N2000 Series

Intel 

8.1.4 PROCHOT# Signal Pin ........................................................................... 119

9

Testability ............................................................................................................ 120

9.1 JTAG Boundary Scan........................................................................................ 120

9.2 TAP Instructions and Opcodes ........................................................................... 121

10 Debug Tool Specifications...................................................................................... 122

Figures

1-1 Intel® Atom™ D2000 series/N2000 series System Block Diagram .................................. 16

3-2 LVDS Signals and Swing Voltage ................................................................................ 40

3-3 LVDS Clock and Data Relationship .............................................................................. 41

3-4 Panel Power Sequencing ........................................................................................... 42

3-5 HDMI Overview........................................................................................................ 43

3-6 DP Overview ........................................................................................................... 44

4-7 Vcc and Icc Processor Loadline................................................................................... 59

4-8 Vcc AC Vs. DC Loadline ............................................................................................. 60

4-9 Definition of Differential Voltage and Differential Voltage Peak-to-Peak............................ 72

4-10Definition of Pre-emphasis ........................................................................................ 72

5-11 Mechanical Drawings ............................................................................................... 74

5-12 Pinmap (Top View, Upper-Left Quadrant) ................................................................... 75

5-13 Pinmap (Top View, Upper-Right Quadrant) ................................................................. 76

5-14 Pinmap (Top View, Lower-Left Quadrant) ................................................................... 77

5-15Pinmap (Top View, Lower-Right Quadrant) .................................................................. 78

6-16Overshoot, Undershoot, and Ringback Illustration ........................................................ 96

7-17Idle Power Management Breakdown of the Processor Cores ......................................... 102

7-18Thread and Core C-state Entry and Exit .................................................................... 102

7-19Processor Core Low-Power States............................................................................. 103

7-20Package C-state Entry and Exit ................................................................................ 108

9-21JTAG Boundary Scan Test Mode Initialization Cycles ................................................... 120

Tables

1-1 Summary of the Resolution of Graphic interface ........................................................... 12

1-2 The Display core clock Frequency by Skus ................................................................... 13

1-3 27 MHz Requirement Range ...................................................................................... 13

2-4 Signal Type ............................................................................................................. 17

2-5 Signal Description Buffer Types.................................................................................. 17

2-6 CPU Legacy Signal ................................................................................................... 18

2-7 Memory Channel A ................................................................................................... 20

2-8 Memory Reference and Compensation......................................................................... 21

2-9 Reset and Miscellaneous Signal .................................................................................. 21

2-10DMI - Processor to Intel NM10 Express Chipset Serial Interface ...................................... 22

2-11PLL Signals ............................................................................................................. 23

2-12Analog Display Signals.............................................................................................. 23

2-13LVDS Signals........................................................................................................... 24

2-14DDI Audio Signals .................................................................................................... 25

2-15DDI Port 0 .............................................................................................................. 27

2-16DDI Port 1 .............................................................................................................. 28

2-17JTAG/ITP Signals ..................................................................................................... 28

2-18Error and Thermal Protection ..................................................................................... 29

2-19Processor Core Power Signals .................................................................................... 29

2-20Power Signals.......................................................................................................... 30

2-21Ground ................................................................................................................... 31

Datasheet - Volume 1 of 2

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