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LC05111CMT

Battery Protection IC for 1-Cell Lithium-Ion with Integrated Power MOSFET

ON Semiconductor 

LC05111CMT

Description of Operation

(1) Normal mode

• LC05111CMT controls charging and discharging by

detecting cell voltage (VCC) and controls S2−S1

current. In case that cell voltage is between

over−discharge detection voltage (Vuv) and

over−charge detection voltage (Vov), and S2−S1 current

is between charge over−current detection current (Ioch)

and discharge over−current detection current (Ioc),

internal power MOS FETs as CHG_SW, DCHG_SW

are all turned ON.

This is the normal mode, and it is possible to be

charged and discharged.

(2) Over−charging mode

• Internal power MOS FET as CHG_SW will be turned

off if cell voltage will get equal to or higher than

over−charge detection voltage (Vov) over the delay

time of over−charging (Tov).

This is the over−charging detection mode.

• The recovery from over−charging will be made after

the following three conditions are all satisfied.

a. Charger is removed from IC.

b. Cell voltage will get lower than over−charge

release voltage (Vovr) over the delay time of

over−charging release (Tovr) due to discharging

through load.

Consequently, internal power MOS FET as CHG_SW will

be turned on and normal mode will be resumed.

• In over−charging mode, discharging over−current

detection is made only when CS pin will get higher

than discharging over−current detection current 2(Ioc2),

because discharge current flows through parasitic diode

of CHG_SW FET.

If CS pin voltage will get higher than discharging

over−current detection current 2 (Ioc2) over the delay

time of discharging over−current 2 (Toc2), discharging

will be shut off, because internal power FETs as

DCHG_SW is turned off.(short−circuit detection mode)

After detecting short−circuit, CS pin will be pulled

down to Vss by internal resistor Rcsd.

The recovery from short circuit detection in over−charging

mode will be made after the following two conditions are

satisfied.

a. Load is removed from IC.

b. CS pin voltage will get equal to or lower than

discharging over−current detection current 2

(Ioc2) due to CS pin pulled down through Rcsd.

Consequently, internal power MOS FET as DCHG_SW will

be turned on, and over−charging detection mode will be

resumed.

(3) Over−discharging mode

• If cell voltage will get lower than over−discharge

detection voltage (Vuv) over the delay time of over−

discharging (Tuv), discharging will be shut off, because

internal power FETs as DCHG_SW is turned off.

This is the over−discharging mode.

After detecting over−discharging, CS pin will be pulled

up to Vcc by internal resistor Rcsu and the bias of

internal circuits will be shut off. (Stand−by mode)

In stand−by mode, operating current is suppressed

under 0.95 mA (max).

• The recovery from stand−by mode will be made by

internal circuits biased after the following two

conditions are satisfied.

a. Charger is connected.

b. VCC level rise more than Over−discharge

release voltage2(Vuvr2) without charger.(Auto

wake−up function)

• If CS pin voltage will get lower than charger detecting

voltage (Vchg) by connecting charger under the

condition that cell voltage is lower than over−discharge

detection voltage, internal power MOS FET as

DCHG_SW is turned on and power dissipation in

power MOS FETs is suppressed.

*In case that charging current is low enough, ripple current

will be appeared at S2 terminal when CS pin voltage is near

by the threshold of charger detecting voltage (Vchg).

It is caused that the two modes, charger detected and charger

not detected (charging through parasitic diodes of

DCHG_SW, is alternately appeared.

• By continuing to be charged, if cell voltage will get

higher than over−discharge detection voltage (Vuvr)

over the delay time of over−discharging (Tuvr), internal

power MOS FETs as DCHG_SW is turned on and

normal mode will be resumed.

• In over−discharge detection mode, charging

over−current detection does not operate.

By continuing to be charged, charging over−current

detection starts to operate after cell voltage goes up

more than over−discharge release voltage (Vuvr).

(4) Discharging over−current detection mode 1

• Internal power MOS FET as DCHG_SW will be turned

off and discharging current will be shut off if CS pin

voltage will get equal to or higher than discharging

over−current detection current (Ioc) over the delay time

of discharging over−current (Toc1).

This is the discharging over−current detection mode 1.

In discharging over−current detection mode 1, CS pin

will be pulled down to Vss with internal resistor Rcsd.

• The recovery from discharging over−current detection

mode will be made after the following two conditions

are satisfied.

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