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LC05111CMT

Battery Protection IC for 1-Cell Lithium-Ion with Integrated Power MOSFET

ON Semiconductor 

LC05111CMT

a. Load is removed from IC.

b. CS pin voltage will get equal to or lower than

discharging over−current release current (Iocr)

over the delay time of discharging over−current

release (Tocr1) due to CS pin pulled down

through Rcsd.

Consequently, internal power MOS FET as DCHG_SW will

be turned on, and normal mode will be resumed.

(5) Discharging over−current detection mode 2 (short circuit

detection)

• Internal power MOS FET as DCHG_SW will be turned

off and discharging current will be shut off if CS pin

voltage will get equal to or higher than discharging

over−current detection current2 (Ioc2) over the delay

time of discharging over−current 2 (Toc2).

This is the short circuit detection mode.

• In short circuit detection mode, CS pin will be pulled

down to Vss by internal resistor Rcsd.

The recovery from short circuit detection mode will be

made after the following two conditions are satisfied.

a. Load is removed from IC.

b. CS pin voltage will get equal to or lower than

discharging over−current release current (Iocr)

over the delay time of discharging over−current

release (Tocr1) due to CS pin pulled down

through Rcsd.

Consequently, internal power MOS FET as DCHG_SW will

be turned on, and normal mode will be resumed.

(6) Charging over−current detection mode

• Internal power MOS FET as CHG_SW will be turned

off and charging current will be shut off if CS pin

voltage will get equal to or lower than charging

over−current detection current (Ioch) over the delay

time of charging over−current (Toch).

This is the charging over−current detection mode.

• The recovery from charging over−current detection

mode will be made after the following two conditions is

satisfied.

a. Charger is removed from IC and CS pin will

get higher by load connected.

b. CS pin voltage will get equal to or higher than

charging over−current release current (Iochr)

over the delay time of charging over−current

release (Tocrh).

Consequently, internal power MOS FET as CHG_SW will

be turned on, and normal mode will be resumed.

*Internal current flows out through CS and S2 terminals.

After charger is removed, it flows through parasitic diode of

CHG_SW FET.

Therefore, CS pin voltage will go up more than charging

over−current release current (Iochr).

So CS pin voltage is not an indispensable condition for

recovery from charging over−current detection.

(7) Available Voltage for 0 V charging

It is the function that the voltage of a connected battery can

charge from the state that became 0 V by self−discharge. The

0 V battery charge start battery charger voltage (Vchg), it fix

a gate of the charge system order FET to the VDD terminal

voltage when it connect a battery charger of the

above−mentioned voltage to PAC+ terminal between PAC−

terminals.

Gate−source voltage of the charge control FET becomes

equal to the turn−on voltage or more due to the charger

voltage, the charging control FET.

To start charging row is turned on.

Discharge control FET is off at this time, the charge current

flows through the internal parasitic diode in the discharging

control FET. It is the normal state battery voltage becomes

the overdischarge release voltage (Vuvr) or more.

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