AD1380KD(RevD) Просмотр технического описания (PDF) - Analog Devices

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AD1380KD
(Rev.:RevD)

Low Cost 16-Bit Sampling ADC

Analog Devices 

AD1380

DESCRIPTION OF OPERATION

On receipt of a CONVERT START command, the AD1380

+15V

converts the voltage at its analog input into an equivalent 16-bit

binary number. This conversion is accomplished as follows: the

16-bit successive-approximation register (SAR) has its 16-bit

OFFSET 10kΩ

ADJ

TO

100kΩ

180kΩ M.F. 180kΩ M.F.

5

22kΩ M.F.

–15V

AD1380

outputs connected to both the device bit output pins and the

corresponding bit inputs of the feedback DAC. The analog

Figure 5. Low Temperature Coefficient Zero Adjustment Circuit

input is successively compared to the feedback DAC output, one

In either adjustment circuit, the fixed resistor connected to

bit at a time (MSB first, LSB last). The decision to keep or reject

Pin 5 should be located close to this pin to keep the pin

each bit is then made at the completion of each bit comparison

connection runs short. Pin 5 is quite sensitive to external noise

period, depending on the state of the comparator at that time.

GAIN ADJUSTMENT

The gain adjustment circuit consists of a 100 ppm/°C poten-

tiometer connected across ±VS with its slider connected

E through a 300 kΩ resistor to Pin 3 (GAIN ADJ) as shown in

Figure 3.

If no external trim adjustment is desired, Pin 5

T (COMPARATOR IN) and Pin 3 may be left open.

+15V

10kΩ

E 100ppm/°C TO

100kΩ

300kΩ

0.01μF

–15V

3 AD1380

Figure 3. Gain Adjustment Circuit (±0.2% FSR)

L ZERO OFFSET ADJUSTMENT

The zero offset adjustment circuit consists of a 100 ppm/°C

potentiometer connected across ±VS with its slider connected

O through a 1.8 MΩ resistor to Pin 5 for all ranges. As shown in

Figure 4, the tolerance of this fixed resistor is not critical; a

carbon composition type is generally adequate. Using a carbon

composition resistor having a −1200 ppm/°C temperature

S coefficient contributes a worst-case offset temperature

coefficient of 32 LSBB14 × 61 ppm/LSB1B 4 × 1200 ppm/°C =

2.3 ppm/°C of FSR, if the offset adjustment potentiometer is set

B at either end of its adjustment range. Since the maximum offset

adjustment required is typically no more than ±16 LSBB14, use of

a carbon composition offset summing resistor typically

contributes no more than 1 ppm/°C of FSR offset temperature

O coefficient.

pickup and should be guarded by ANALOG COMMON.

TIMING

The timing diagram is shown in Figure 6. Receipt of a

CONVERT START signal sets the STATUS flag, indicating

conversion in progress. This, in turn, removes the inhibit

applied to the gated clock, permitting it to run through

17 cycles. All the SAR parallel bits, STATUS flip-flops and the

gated clock inhibit signal are initialized on the trailing edge of

the CONVERT START signal. At time t0, B1 is reset and B2 to

B16 are set unconditionally. At t1, the Bit 1 decision is made

(keep) and Bit 2 is reset unconditionally. This sequence

continues until the Bit 16 (LSB) decision (keep) is made at t16.

The STATUS flag is reset, indicating that the conversion is

complete and the parallel output data is valid. Resetting the

STATUS flag restores the gated clock inhibit signal, forcing the

clock output to the low Logic 0 state. Note that the clock

remains low until the next conversion.

Corresponding parallel data bits become valid on the same

positive-going clock edge.

(1)

CONVERT

START

MAXIMUM THROUGHPUT TIME

CONVERSION TIME (2)

tACQUISITION

INTERNAL

CLOCK

STATUS

MSB

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16

(3)

0

(4) t17

1

1

0

0

1

1

1

0

+15V

BIT 10

BIT 11

1

1

10kΩ

TO

100kΩ

1.8MΩ

5 AD1380

BIT 12

BIT 13

BIT 14

1

1

0

–15V

BIT 15

LSB

MSB

1

0

LSB

Figure 4. Zero Offset Adjustment Circuit (±0.3% FSR)

01 1 0 01 1 1 0 1 1 1 1 0 1 0

An alternate offset adjustment circuit, which contributes a

negligible offset temperature coefficient if metal film resistors

(temperature coefficient <100 ppm/°C) are used, is shown in

NOTES:

1. THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A

CONVERSION. THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE

CONVERT COMMAND.

2. tCONV = 14μs (MAX), tACQ = 6μs (MAX).

3. MSB DECISION.

4. CLOCK REMAINS LOW AFTER LAST BIT DECISION.

Figure 5.

Figure 6. Timing Diagram (Binary Code 0110011101 111010)

Rev. D | Page 7 of 12

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