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74LVC823AD,112 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LVC823AD,112 Datasheet PDF : 21 Pages
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Nexperia
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
MR 11
GND 12
24 VCC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
823
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
13 CP
001aaa845
Fig 5. Pin configuration SO24 and (T)SSOP24
terminal 1
index area
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
MR 11
823
GND(1)
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
001aaa846
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DHVQFN24
5.2 Pin description
Table 2.
Pin
OE
MR
D[0:8]
Q[0:8]
CP
CE
GND
VCC
Pin description
Name
1
11
2, 3, 4, 5, 6, 7, 8, 9, 10
23, 22, 21, 20, 19, 18, 17, 16, 15
13
14
12
24
Description
output enable input (active LOW)
master reset input (active LOW)
data input
3-state flip-flop output
clock input (LOW to HIGH; edge-triggered)
clock enable input (active LOW)
ground (0 V)
supply voltage
74LVC823A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© Nexperia B.V. 2017. All rights reserved
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