74HC175 Просмотр технического описания (PDF) - NXP Semiconductors.
Номер в каталоге
Компоненты Описание
производитель
74HC175 Datasheet PDF : 19 Pages
| |||
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 8 April 2014
Product data sheet
1. General description
The 74HC175; 74HCT175 are quad positive edge-triggered D-type flip-flops with
individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is
stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and
outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are
required and the clock and master reset are common to all storage elements.
2. Features and benefits
Input levels:
For 74HC175: CMOS level
For 74HCT175: TTL level
Four edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74HC175N
40 C to +125 C DIP16
74HCT175N
74HC175D
40 C to +125 C SO16
74HCT175D
74HC175DB 40 C to +125 C SSOP16
74HCT175DB
74HC175PW 40 C to +125 C TSSOP16
74HCT175PW
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Share Link: 