74AHCT08PW,118 Просмотр технического описания (PDF) - NXP Semiconductors.
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74AHCT08PW,118 Datasheet PDF : 14 Pages
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Nexperia
4. Functional diagram
74AHC08; 74AHCT08
Quad 2-input AND gate
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna222
Fig 1. Logic symbol
1
&
3
2
4
&
6
5
9
&
8
10
12
&
11
13
mna223
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna221
Fig 3. Logic diagram (one gate)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
08
11 4Y
10 3B
9 3A
8 3Y
001aac945
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
08
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aac946
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
74AHC_AHCT08_3
Product data sheet
Rev. 03 — 14 November 2007
© Nexperia B.V. 2017. All rights reserved
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