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V961PBC-40REVB2 Просмотр технического описания (PDF) - QuickLogic Corporation

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V961PBC-40REVB2
QuickLogic
QuickLogic Corporation QuickLogic
V961PBC-40REVB2 Datasheet PDF : 16 Pages
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V961PBC
4.0 AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev.
2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V
signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification.
4.1 PCI Bus Timings
Table 10: PCI Bus Signals AC Operating Specifications
Symbol Parameter
Condition
Min
Max Units Notes
IOH(AC)
0V<VOUT1.4V
-44
Switching
mA
1
current high
1.4V<VOUT<2.4V
-44+(VOUT-1.4)/0.024
Equation
A
mA
1, 2, 3
IOL(AC)
(Test point)
Switching
current low
VOUT=3.1V
VOUT2.2V
2.2V>VOUT>0.55
95
VOUT/0.023
-142
mA
3
mA
1
Equation
B
mA
1, 3
(Test point)
ICL
Low clamp
current
VOUT=0.71
-5<VIN-1
206
mA
3
-25+(VIN+1)/0.015
mA
tR
Unloaded
output rise time
0.4V to 2.4V
1
5
V/ns
4
tF
Unloaded
output fall time
2.4V to 0.4V
1
5
V/ns
4
Notes:
1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and
RST which are system outputs. “Switching Current High” specifications are not relevant to open drain outputs
such as SERR and INTA-INTD.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive
point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow
for an optional N-channel pull-up.
3. Maximum current requirements are met as drivers pull beyond the first step voltage (AC drive point). Equations
defining these maximums (A and B) are provided with the respective V/I curves given in the PCI Spec. The equa-
tion defined maxima is met by design.
4. The minimum slew rate (slowest signal edge) is met by the PCI drivers. The maximum slew rate (fastest signal
edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum
guideline could occur, and should ensure that signal integrity modeling accounts for this.
Equation A: IOH = 11.9·(VOUT - 5.25V)·(VOUT + 2.45V) for VCC > VOUT > 3.1V
Equation B: IOL = 78.5·VOUT(4.4V - VOUT) for 0V < VOUT < 0.71V
Copyright © 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
11

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