V363EPC Просмотр технического описания (PDF) - QuickLogic Corporation
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V363EPC Datasheet PDF : 23 Pages
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Pin Descriptions and Pinouts
Table 4: Signal Descriptions: Processor Mode Dependent
De-Multiplexed A/D
Multiplexed A/D
Type
AM29030/40 i960Cx/Hx i960Jx i960Sx
ID[31:0]
LA[31:2]
BWE[3:0]
R/W
—
LD[31:0] LAD[31:0] LAD[15:0] I/O4
LA[31:2]
BE[3:0]
W/R
—
LA[5:2]
BE[3:0]
W/R
ALE
LA[31:16]
LA[5:2]
I/O4
BE[1:0] I/O4
W/R
I/O4
ALE
I/O4
LREQ
ADS
ADS
AS
I/O4
RDY
LBREQ
LBGRT
LPAR[3:0]
BURST
READY RDYRCY READY I/O4
HOLD
HOLD
HOLD O4
HOLDA HOLDA HOLDA I
LPAR[3:0] LPAR[3:0] LPAR[1:0] I/O4
BLAST BLAST BLAST I/O4
ERR
BTERM BTERM
—
I/O4
LINT
LRST
MEMCLK
LINT
LRST
LCLK
LINT
LRST
LCLK
LINT
O4
LRST I/O4
LCLK
I
1. The reset state is ‘H’ in AM29030/40 mode.
Reset
State
Z
Z
Z
Z
Z
Z
Z
L1
Z
Z
Z
H
L/Z
Description
De-multiplexed data bus.
Multiplexed address and data bus.
Address Bus LA[5:2] are output only in
Multiplexed A/D mode.
Byte Enables
Read-Write strobe.
Address Latch Enable
Address Strobe is asserted low to indicate
the beginning of a bus cycle; interpreted as
LREQ in AM29030/40 mode.
Data Ready
Bus Mastership Request
Bus Mastership Grant
Data Parity
BURST: Burst Request
BLAST: Burst Last
ERR: Bus Time-out
BTERM: Burst Terminate
Local Interrupt Request
Local Bus RESET
Local Bus Clock
6
V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101
© 2000 V3 Semiconductor Corp.
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